基于FPGA的即时通讯工具.docx
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基于FPGA的即时通讯工具
基于FPGA的即时通讯工具
成员：
赵志强，王再成，宫盐坤，高彩丽
成员:
马超，孙建永，张鹏
日期：
2011年1月1日
组内分工
PS2键盘输入
赵志强，王再成，宫盐坤，高彩丽
LCD显示
孙建永，张鹏
Uart通信
马超
各模块整合
孙建永，张鹏
代码：
ps2键盘上输入（赵志强，王再成，宫盐坤，高彩丽）
moduleps2_scan（
clk,
rst_n,
ps2_clk,
ps2_data,
data_out_8bit,
ps2_state,
valid_flag）;
inputclk;
inputrst_n;
inputps2_clk;//PS2接口时钟信号
inputps2_data;//PS2接口数据信号
output[7:
0]data_out_8bit;//1byte键值只做简单的按键扫描
outputps2_state;//键盘当前状态ps2_state=1表示有键被按下
outputvalid_flag;
//reg[7:
0]data_out_8bit;
//*************************************************************
regps2_clk1,ps2_clk2,ps2_clk3;
always@（posedgeclkornegedgerst_n）
if（~rst_n）begin
ps2_clk1<=1'b0;
ps2_clk2<=1'b0;
ps2_clk3<=1'b0;
end
elsebegin
ps2_clk1<=ps2_clk;
ps2_clk2<=ps2_clk1;
ps2_clk3<=ps2_clk2;
end
wireneg_clkps2;
assignneg_clkps2=~ps2_clk2&ps2_clk3;
//**************************************************************
regps2_state;
reg[7:
0]ps2_byte_r;
reg[7:
0]temp_data;
reg[3:
0]num;//当前接收数据寄存?
reg[3:
0]num;
always@（posedgeclkornegedgerst_n）begin
if（!
rst_n）begin
num<=4'd0;
temp_data<=8'd0;
ps2_state<=1'b0;
end
elseif（neg_clkps2）begin//ps2k_clk的下降沿接收键盘数据
case（num）
4'd0:
begin
num<=num+1'b1;
ps2_state<=1'b1;
end
4'd1:
begin
num<=num+1'b1;
temp_data[0]<=ps2_data;//bit0
end
4'd2:
begin
num<=num+1'b1;
temp_data[1]<=ps2_data;//bit1
end
4'd3:
begin
num<=num+1'b1;
temp_data[2]<=ps2_data;//bit2
end
4'd4:
begin
num<=num+1'b1;
temp_data[3]<=ps2_data;//bit3
end
4'd5:
begin
num<=num+1'b1;
temp_data[4]<=ps2_data;//bit4
end
4'd6:
begin
num<=num+1'b1;
temp_data[5]<=ps2_data;//bit5
end
4'd7:
begin
num<=num+1'b1;
temp_data[6]<=ps2_data;//bit6
end
4'd8:
begin
num<=num+1'b1;
temp_data[7]<=ps2_data;//bit7
end
4'd9:
num<=num+1'b1;//奇偶校验位不做处理
4'd10:
begin
num<=4'd0;
ps2_state<=1'b0;
end
default:
begin
num<=4'd0;
temp_data<=8'd0;
ps2_state<=1'b0;
end
endcase
end
end
//******************************************************
regkey_f0;
regreg_valid_flag;
always@（posedgeclkornegedgerst_n）
if（!
rst_n）begin
key_f0<=1'b0;
reg_valid_flag<=1'b0;
endelsebegin
if（num==4'd10）begin//刚传送完一个字节数据
if（temp_data==8'hf0）begin
key_f0<=1'b1;
reg_valid_flag<=1'b1;
endelsebegin
if（~key_f0）begin
ps2_byte_r<=temp_data;//锁存当前键值
reg_valid_flag<=1'b0;
endelsebegin
key_f0<=1'b0;
reg_valid_flag<=1'b0;
end
end
endelsebegin
reg_valid_flag<=1'b0;
end
end
//******************************************************************
reg[7:
0]ps2_asci;//接SCII码
always@（ps2_byte_r）begin
case（ps2_byte_r）//键值转换为ASCII码
8'h15:
ps2_asci<=8'h51;//Q
8'h1d:
ps2_asci<=8'h57;//W
8'h24:
ps2_asci<=8'h45;//E
8'h2d:
ps2_asci<=8'h52;//R
8'h2c:
ps2_asci<=8'h54;//T
8'h35:
ps2_asci<=8'h59;//Y
8'h3c:
ps2_asci<=8'h55;//U
8'h43:
ps2_asci<=8'h49;//I
8'h44:
ps2_asci<=8'h4f;//O
8'h4d:
ps2_asci<=8'h50;//P
8'h1c:
ps2_asci<=8'h41;//A
8'h1b:
ps2_asci<=8'h53;//S
8'h23:
ps2_asci<=8'h44;//D
8'h2b:
ps2_asci<=8'h46;//F
8'h34:
ps2_asci<=8'h47;//G
8'h33:
ps2_asci<=8'h48;//H
8'h3b:
ps2_asci<=8'h4a;//J
8'h42:
ps2_asci<=8'h4b;//K
8'h4b:
ps2_asci<=8'h4c;//L
8'h1z:
ps2_asci<=8'h5a;//Z
8'h22:
ps2_asci<=8'h58;//X
8'h21:
ps2_asci<=8'h43;//C
8'h2a:
ps2_asci<=8'h56;//V
8'h32:
ps2_asci<=8'h42;//B
8'h31:
ps2_asci<=8'h4e;//N
8'h3a:
ps2_asci<=8'h4d;//M
8'h16:
ps2_asci<=8'h31;//1
8'h1E:
ps2_asci<=8'h32;//2
8'h26:
ps2_asci<=8'h33;//3
8'h25:
ps2_asci<=8'h34;//4
8'h2E:
ps2_asci<=8'h35;//5
8'h36:
ps2_asci<=8'h36;//6
8'h3D:
ps2_asci<=8'h37;//7
8'h3E:
ps2_asci<=8'h38;//8
8'h46:
ps2_asci<=8'h39;//9
8'h45:
ps2_asci<=8'h30;//0
8'h5A:
ps2_asci<=8'h0D;//Enter
default:
ps2_asci<=8'h00;
endcase
end
regprev_valid_sig_0;
regprev_valid_sig_1;
always@（posedgeclk）begin
prev_valid_sig_0<=reg_valid_flag;
prev_valid_sig_1<=prev_valid_sig_0;
end
regvalid_flag;
//assignvalid_flag=prev_valid_sig_0&~prev_valid_sig_1;
always@（posedgeclk）begin
if（valid_flag==1'b1）begin
valid_flag<=1'b0;
endelse
valid_flag<=prev_valid_sig_0&~prev_valid_sig_1;
end
assigndata_out_8bit=ps2_asci;
endmodule
LCD显示（孙建永，张鹏）：
modulelcd（sf_d,
lcd_e,
lcd_rs,
lcd_rw,
rst,
clk,
state,
idle_h,
if_write,
data_input_8bit）;
inputrst;
inputclk;
inputif_write;
input[7:
0]data_input_8bit;
outputidle_h;
outputlcd_e;
outputlcd_rs;
outputlcd_rw;
output[3:
0]sf_d;
output[5:
0]state;
reglcd_e;
reglcd_rs;
reglcd_rw;
reg[3:
0]sf_d;
regidle_h;
parameter
data_stable_wait=2,
lcd_e_h_wait=12,
inter_wait=50,
sta_between_wait=2000,
after_init_wait=2000,
after_cln_dis_wait=92000,
sta_begin_wait=750000,
sta_init_1_wait=205000,
sta_init_2_wait=5000,
sta_init_3_wait=2000,
sta_init_4_wait=2000;
parameter
sta_begin=6'b00_0000,
sta_init_1_1=6'b00_0001,
sta_init_1_begin_lcd_e_h_wait=6'b00_0010,
sta_init_1_end=6'b00_0011,
sta_init_2_begin=6'b00_0100,
sta_init_2_end=6'b00_0101,
sta_init_3_begin=6'b00_0110,
sta_init_3_end=6'b00_0111,
sta_init_4_begin=6'b00_1000,
sta_init_4_lcd_e_h_wait=6'b00_1001,
sta_after_init_4_wait=6'b00_1010,
sta_function_set_1=6'b00_1011,
sta_function_set_1_lcd_e_h_wait=6'b00_1100,
sta_function_set_inter_wait=6'b00_1101,
sta_function_set_2=6'b00_1110,
sta_function_set_2_lcd_e_h_wait=6'b00_1111,
sta_after_function_set_wait=6'b01_0000,
sta_entry_mode_set_1=6'b01_0001,
sta_entry_mode_set_1_lcd_e_h_wait=6'b01_0010,
sta_entry_mode_set_inter_wait=6'b01_0011,
sta_entry_mode_set_2=6'b01_0100,
sta_entry_mode_set_2_lcd_e_h_wait=6'b01_0101,
sta_after_entry_mode_set_wait=6'b01_0110,
sta_dis_on_off_1=6'b01_0111,
sta_dis_on_off_1_lcd_e_h_wait=6'b01_1000,
sta_dis_on_off_inter_wait=6'b01_1001,
sta_dis_on_off_2=6'b01_1010,
sta_dis_on_off_lcd_e_h_wait=6'b01_1011,
sta_after_dis_on_off=6'b01_1100,
sta_cln_dis_1=6'b01_1101,
sta_cln_dis_1_lcd_e_h_wait=6'b01_1110,
sta_cln_dis_inter_wait=6'b01_1111,
sta_cln_dis_2=6'b10_0000,
sta_cln_dis_2_lcd_e_h_wait=6'b10_0001,
sta_after_cln_dis_wait=6'b10_0010,
sta_write_addr_1=6'b10_0011,
sta_write_addr_1_lcd_e_h_wait=6'b10_0100,
sta_write_addr_inter_wait=6'b10_0101,
sta_write_addr_2=6'b10_0110,
sta_write_addr_2_lcd_e_h_wait=6'b10_0111,
sta_after_write_addr=6'b10_1000,
sta_write_data_1=6'b10_1001,
sta_write_data_1_lcd_e_h_wait=6'b10_1010,
sta_write_data_inter_wait=6'b10_1011,
sta_write_data_2=6'b10_1100,
sta_write_data_2_lcd_e_h_wait=6'b10_1101,
sta_write_idle=6'b10_1110,
sta_write_begin=6'b10_1111,
sta_write_end_wait=6'b11_0000,
sta_detect_data=6'b11_0001;
parameter
SET_HIGH_ADDR=8'b1000_0000,
SET_LOW_ADDR=8'b1100_0000,
CLN=8'b1111_1100;
reg[5:
0]state;
reg[19:
0]cnt;
reg[7:
0]data_write_8bit;
always@（posedgeclk）begin
lcd_rw<=1'b0;
end
always@（posedgeclkornegedgerst）begin
if（rst==1'b0）begin
state<=sta_begin;
lcd_rs<=1'b0;
cnt<=0;
idle_h<=1'b0;
endelsebegin
case（state）
sta_begin:
begin
if（cnt==sta_begin_wait）begin
cnt<=0;
state<=sta_function_set_1;
idle_h<=1'b0;
endelsecnt<=cnt+1;
end
sta_function_set_1:
begin
if（cnt==data_stable_wait）begin
lcd_e<=1'b1;
state<=sta_function_set_1_lcd_e_h_wait;
cnt<=0;
endelsebegin
cnt<=cnt+1;
sf_d<=4'b0010;
lcd_rs<=1'b0;
end
end
sta_function_set_1_lcd_e_h_wait:
begin
if（cnt==lcd_e_h_wait）begin
state<=sta_function_set_inter_wait;
lcd_e<=1'b0;
cnt<=0;
endelsecnt<=cnt+1;
end
sta_function_set_inter_wait:
begin
if（cnt==inter_wait）begin
state<=sta_function_set_2;
cnt<=0;
endelsecnt<=cnt+1;
end
sta_function_set_2:
begin
if（cnt==data_stable_wait）begin
lcd_e<=1'b1;
state<=sta_function_set_2_lcd_e_h_wait;
cnt<=0;
endelsebegin
cnt<=cnt+1;
sf_d<=4'b1000;
end
end
sta_function_set_2_lcd_e_h_wait:
begin
if（cnt==lcd_e_h_wait）begin
state<=sta_after_function_set_wait;
lcd_e<=1'b0;
cnt<=0;
endelsecnt<=cnt+1;
end
sta_after_function_set_wait:
begin
if（cnt==sta_between_wait）begin
state<=sta_entry_mode_set_1;
cnt<=0;
endelsecnt<=cnt+1;
end
sta_entry_mode_set_1:
begin
if（cnt==data_stable_wait）begin
state<=sta_entry_mode_set_1_lcd_e_h_wait;
lcd_e<=1'b1;
cnt<=0;
endelsebegin
cnt<=cnt+1;
sf_d<=4'b0000;
end
end
sta_entry_mode_set_1_lcd_e_h_wait:
begin
if（cnt==lcd_e_h_wait）begin
state<=sta_entry_mode_set_inter_wait;
lcd_e<=1'b0;
cnt<=0;
endelsecnt<=cnt+1;
end
sta_entry_mode_set_inter_wait:
begin
if（cnt==inter_wait）begin
state<=sta_entry_mode_set_2;
cnt<=0;
endelsecnt<=cnt+1;
end
sta_entry_mode_set_2:
begin
if（cnt==data_stable_wait）begin
state<=sta_entry_mode_set_2_lcd_e_h_wait;
lcd_e<=1'b1;
cnt<=0;
endelsebegin
cnt<=cnt+1;
sf_d<=4'b0110;
end
end
sta_entry_mode_set_2_lcd_e_h_wait:
begin
if（cnt==lcd_e
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