ExceptionandInterruptHandlinginARM.docx

1、ExceptionandInterruptHandlinginARMException and Interrupt Handling in ARMArchitectures and Design Methods for Embedded SystemsSummer Semester 2006Author: Ahmed Fathy Mohammed AbdelrazekAdvisor: Dominik LckeAbstractWe discuss exceptions and interrupt handling techniques in ARM processors and see how

2、the ARM architecture works in this area to know how are these techniques suitable for embedded systems to achieve the time constraints and safety requirements. Exception and interrupt handling is a critical issue since it affect directly the speed of the system and how fast does the system respond t

3、o external events and how does it deal with more than one external event at the same time by assigning priorities to these events.Table of contentsAbstract.2Table of contents.2List of Figures.3Abbreviations.31 Introduction.41.1 ARM modes of operation.41.2 ARM Register set.5.62 ARM Exceptions.62.1 Ve

4、ctor Table.72.2 Exception priorities.82.3 Link Register Offset.82.4 Entering and exiting an exception handler.93 Interrupts.93.1 How are interrupts assigned?.93.2 Interrupt Latency.103.3 IRQ and FIQ exceptions.103.4 Interrupt stack.104 Interrupt handling schemes.114.1 Non-nested interrupt handling.1

5、14.1.1 Non-nested interrupt handling summery:.124.2 Nested interrupt handling.124.2.1 Nested interrupt handling summery:.134.3 Prioritized simple interrupt handling.134.3.1 Prioritized simple interrupt handling summery:.144.4 Other schemes.155 Final remarks.16Which interrupt handling scheme to use?.

6、16References.17List of FiguresFigure 1: Register Organization in ARM 5.6Figure 2 An exact vector table with the branching instruction5.7Figure 3 Typical Memory Layouts.11Figure 4 Simple non nested interrupt handlers.12Figure 5 Nested Interrupt Handling.13Figure 6 Priority Interrupt Handler 1.14Abbre

7、viationsISR Interrupt Service RoutineInterruptRequestFIQ Fast Interrupt RequestARM Advanced RISC MachinesRISC Reduced Instruction Set ComputersCPSR Current Program Status RegisterSPSR Saved Program Status RegisterRegisterRegisterDMA Direct Memory Access1 IntroductionExceptions are so important in em

8、bedded systems, without exception the development of systems would be a very complex task. With exceptions we can detect bugs in the application, errors in memory access and finally debug it by placing breakpoints and building the program with debugging information.Interrupts which are kinds of exce

9、ptions are essential in embedded systems. It enables the system to deal with external events by receiving interrupt signals telling the CPU that there is something to be done instead of the alternative way of doing the same operation by the pooling mechanism which wastes the CPU time in looping fore

10、ver checking some flags to know that the event occurred.Due to the fact that systems are going more complex day after day, we have nowadays systems with more than one interrupt source. That is why an interrupt handling scheme is needed to define how different cases will be handled. We may need prior

11、ities to be assigned to different interrupts and in some other cases we may need nested handling capabilities.We introduce the ARM processor itself to see its different modes of operation and then we have an overview of the register set. This is because dealing with interrupts and exceptions causes

12、the ARM core to switch between these modes and copy some of the registers into other registers to safe the core state before switching to the new mode. In the next chapter we introduce exceptions and see how the ARM processor handles exceptions. In the third chapter we define interrupts and discuss

13、mechanisms of interrupt handling on ARM. In the forth chapter we provide a set of standard interrupt handling schemes. And finally some remarks regarding these schemes and which one is suitable to which application.The main source of information provided in this paper is mainly the book “ARM System

14、Developers Guide” 1.1.1 ARM modes of operationThe ARM processor internally has 7 different modes of operation, they are as follows; User mode: It is used for normal program execution state, FIQ mode: This mode is used for interrupts requiring fast response and low latency like for example data trans

15、fer with DMA, IRQ mode: This mode is used for general interrupt services, Supervisor mode: This mode is used when operating system support is needed where it works as protected mode, Abort mode: selected when data or instruction fetch is aborted, system mode: Operating system privilege mode for user

16、s and undefined mode: When undefined instruction is fetched. The following table summarizes the 7 modes:Processor ModeUser (usr)FIQ (fiq)IRQ (irq)Supervisor (svc)Abort (abt)Undefined (und)System (sys)Description Normal program execution mode Fast data processing mode For general purpose interrupts A

17、 protected mode for the operating system When data or instruction fetch is aborted For undefined instructions Operating system privileged mode1.2 ARM Register setRegister structure in ARM depends on the mode of operation. For example we have 16 (32-bit) registers named from R0 to R15 in ARM mode (us

18、r).Registers R0 to R12 are general purpose registers, R13 is stack pointer (SP), R14 is subroutine link register and R15 is program counter (PC).R16 is the current program status register (CPSR) this register is shared between all modes and it is used by the ARM core all the time and it plays a main

19、 role in the process of switching between modes.In other modes some of these 16 registers are visible and can be accessed and some others are not visible and cant be accessed. Also some registers are available with the same name but as another physical register in memory which is called (banked), ex

20、istence of such banked registers decreases the effort needed when context switching is required since the new mode has its own physical register space and no need to store the old modes register values.So in ARM7 we have a total of 37 physical registers and the following figure shows the ARM7 regist

21、er set.More bankedregisters, sois fasterFigure 1: Register Organization in ARM 5As we can see the banked registers are marked with the gray colour. We can notice that in the FIQ mode there are more banked registers, this is to speed up the context switching since there will be no need to store many registers when switching to the FIQ mode. We may need only to store the values of registers r0 to r7 if the FIQ handler needs to use those registers, but registers r8_fiq to r14_fiq are specific registers for the FIQ mode and