ExceptionandInterruptHandlinginARM.docx

ExceptionandInterruptHandlinginARM.docx

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ExceptionandInterruptHandlinginARM

ExceptionandInterruptHandlinginARM

ArchitecturesandDesignMethodsforEmbeddedSystems

SummerSemester2006

Author:

AhmedFathyMohammedAbdelrazek

Advisor:

DominikLücke

Abstract

WediscussexceptionsandinterrupthandlingtechniquesinARMprocessorsandseehowtheARMarchitectureworksinthisareatoknowhowarethesetechniquessuitableforembeddedsystemstoachievethetimeconstraintsandsafetyrequirements.Exceptionandinterrupthandlingisacriticalissuesinceitaffectdirectlythespeedofthesystemandhowfastdoesthesystemrespondtoexternaleventsandhowdoesitdealwithmorethanoneexternaleventatthesametimebyassigningprioritiestotheseevents.

Tableofcontents

Abstract......................................................................................................................................2

Tableofcontents........................................................................................................................2

ListofFigures............................................................................................................................3

Abbreviations.............................................................................................................................3

1Introduction........................................................................................................................4

1.1ARMmodesofoperation......................................................................................4

1.2ARMRegisterset...................................................................................................5

................................................................................................................................................6

2ARMExceptions................................................................................................................6

2.1VectorTable..........................................................................................................7

2.2Exceptionpriorities................................................................................................8

2.3LinkRegisterOffset...............................................................................................8

2.4Enteringandexitinganexceptionhandler.............................................................9

3Interrupts............................................................................................................................9

3.1Howareinterruptsassigned?

.................................................................................9

3.2InterruptLatency..................................................................................................10

3.3IRQandFIQexceptions......................................................................................10

3.4Interruptstack......................................................................................................10

4Interrupthandlingschemes..............................................................................................11

4.1Non-nestedinterrupthandling.............................................................................11

4.1.1Non-nestedinterrupthandlingsummery:

....................................................................12

4.2Nestedinterrupthandling.....................................................................................12

4.2.1Nestedinterrupthandlingsummery:

...........................................................................13

4.3Prioritizedsimpleinterrupthandling...................................................................13

4.3.1Prioritizedsimpleinterrupthandlingsummery:

..........................................................14

4.4Otherschemes......................................................................................................15

5Finalremarks....................................................................................................................16

Whichinterrupthandlingschemetouse?

............................................................................16

References................................................................................................................................17

ListofFigures

Figure1:

RegisterOrganizationinARM[5]...............................................................................6

Figure2Anexactvectortablewiththebranchinginstruction[5]...............................................7

Figure3TypicalMemoryLayouts...........................................................................................11

Figure4Simplenonnestedinterrupthandlers.........................................................................12

Figure5NestedInterruptHandling.........................................................................................13

Figure6PriorityInterruptHandler[1].......................................................................................14

Abbreviations

ISRInterruptServiceRoutine

Interrupt

Request

FIQFastInterruptRequest

ARMAdvancedRISCMachines

RISCReducedInstructionSetComputers

CPSRCurrentProgramStatusRegister

SPSRSavedProgramStatusRegister

Register

Register

DMADirectMemoryAccess

1Introduction

Exceptionsaresoimportantinembeddedsystems,withoutexceptionthedevelopmentofsystemswouldbeaverycomplextask.Withexceptionswecandetectbugsintheapplication,errorsinmemoryaccessandfinallydebugitbyplacingbreakpointsandbuildingtheprogramwithdebugginginformation.

Interruptswhicharekindsofexceptionsareessentialinembeddedsystems.ItenablesthesystemtodealwithexternaleventsbyreceivinginterruptsignalstellingtheCPUthatthereissomethingtobedoneinsteadofthealternativewayofdoingthesameoperationbythepoolingmechanismwhichwastestheCPUtimeinloopingforevercheckingsomeflagstoknowthattheeventoccurred.

Duetothefactthatsystemsaregoingmorecomplexdayafterday,wehavenowadayssystemswithmorethanoneinterruptsource.Thatiswhyaninterrupthandlingschemeisneededtodefinehowdifferentcaseswillbehandled.Wemayneedprioritiestobeassignedtodifferentinterruptsandinsomeothercaseswemayneednestedhandlingcapabilities.

WeintroducetheARMprocessoritselftoseeitsdifferentmodesofoperationandthenwehaveanoverviewoftheregisterset.ThisisbecausedealingwithinterruptsandexceptionscausestheARMcoretoswitchbetweenthesemodesandcopysomeoftheregistersintootherregisterstosafethecorestatebeforeswitchingtothenewmode.InthenextchapterweintroduceexceptionsandseehowtheARMprocessorhandlesexceptions.InthethirdchapterwedefineinterruptsanddiscussmechanismsofinterrupthandlingonARM.Intheforthchapterweprovideasetofstandardinterrupthandlingschemes.Andfinallysomeremarksregardingtheseschemesandwhichoneissuitabletowhichapplication.

Themainsourceofinformationprovidedinthispaperismainlythebook“ARMSystemDeveloper’sGuide”[1].

1.1ARMmodesofoperation

TheARMprocessorinternallyhas7differentmodesofoperation,theyareasfollows;Usermode:

Itisusedfornormalprogramexecutionstate,FIQmode:

ThismodeisusedforinterruptsrequiringfastresponseandlowlatencylikeforexampledatatransferwithDMA,IRQmode:

Thismodeisusedforgeneralinterruptservices,Supervisormode:

Thismodeisusedwhenoperatingsystemsupportisneededwhereitworksasprotectedmode,Abortmode:

selectedwhendataorinstructionfetchisaborted,systemmode:

Operatingsystemprivilegemodeforusersandundefinedmode:

Whenundefinedinstructionisfetched.Thefollowingtablesummarizesthe7modes:

ProcessorMode

User（usr）

FIQ（fiq）

IRQ（irq）

Supervisor（svc）

Abort（abt）

Undefined（und）

System（sys）

DescriptionNormalprogramexecutionmodeFastdataprocessingmodeForgeneralpurposeinterruptsAprotectedmodefortheoperatingsystemWhendataorinstructionfetchisabortedForundefinedinstructionsOperatingsystemprivilegedmode

1.2ARMRegisterset

RegisterstructureinARMdependsonthemodeofoperation.Forexamplewehave16（32-bit）registersnamedfromR0toR15inARMmode（usr）.

RegistersR0toR12aregeneralpurposeregisters,R13isstackpointer（SP）,R14issubroutinelinkregisterandR15isprogramcounter（PC）.

R16isthecurrentprogramstatusregister（CPSR）thisregisterissharedbetweenallmodesanditisusedbytheARMcoreallthetimeanditplaysamainroleintheprocessofswitchingbetweenmodes.

Inothermodessomeofthese16registersarevisibleandcanbeaccessedandsomeothersarenotvisibleandcan’tbeaccessed.Alsosomeregistersareavailablewiththesamenamebutasanotherphysicalregisterinmemorywhichiscalled（banked）,existenceofsuchbankedregistersdecreasestheeffortneededwhencontextswitchingisrequiredsincethenewmodehasitsownphysicalregisterspaceandnoneedtostoretheoldmode’sregistervalues.

SoinARM7wehaveatotalof37physicalregistersandthefollowingfigureshowstheARM7registerset.

Morebanked

registers,so

isfaster

Figure1:

RegisterOrganizationinARM[5]

Aswecanseethebankedregistersaremarkedwiththegraycolour.WecannoticethatintheFIQmodetherearemorebankedregisters,thisistospeedupthecontextswitchingsincetherewillbenoneedtostoremanyregisterswhenswitchingtotheFIQmode.Wemayneedonlytostorethevaluesofregistersr0tor7iftheFIQhandlerneedstousethoseregisters,butregistersr8_fiqtor14_fiqarespecificregistersfortheFIQmodeand