VHDL数字钟代码Word文件下载.docx

1、 ten : out std_logic_vector（7 downto 0）; one : out std_logic_vector（7 downto 0） component i24bcd in integer range 0 to 23; signal carry1,carry2 : signal abin1,abin2 : integer range 0 to 59; signal abin3 : integer range 0 to 23; signal clk_1h : signal sh,sl,mh,ml,hh,hl : std_logic_vector（7 downto 0）;

2、 signal cnt : integer range 0 to 5 :=0;begin process（clk）-分频为1hz constant counter_len:integer:=19999999; variable cnt:integer range 0 to counter_len; begin if clkevent and clk=1 then if cnt=counter_len then cnt: else=cnt+1; end if; case cnt is when 0 to counter_len/2=clk_1h end case; end process; pr

3、ocess（clk） variable cnt1 : integer range 0 to 200; variable cnt2 : integer range 0 to 10; if cnt1=200 then cnt1: if cnt2=10 then cnt2: if（cnt=5）then cnt duan=000001data_o000010=sh; when 2 =000100=ml; when 3 =001000=mh; when 4 =010000=hl; when 5 =100000=hh; when others=duanclk_1h,rst=reset,times=abin

4、1,full=carry1）; u2 :carry1,rst=abin2,full=carry2）; u3 : count24 port map（carry=carry2,rst=abin3）; u4 : i60bcd port map（interg=abin1,ten=sh,one=sl）; u5 :abin2,ten=mh,one=ml）; u6 : i24bcd port map（interg=abin3,ten=hh,one=hl）;entity count60 is-分，秒计数器architecture a of count60 is signal time_s : process（

5、rst,carry） if rst= time_s full elsif rising_edge（carry） then if time_s=59 then=time_s+1; times=time_s;library ieee;entity count24 is-时计数器architecture a of count24 is -full one11111001 when 2|12|22|32|42|52 =10100100 when 3|13|23|33|43|53 =10110000 when 4|14|24|34|44|54 =10011001 when 5|15|25|35|45|5

6、5 =10010010 when 6|16|26|36|46|56 =10000011 when 7|17|27|37|47|57 =11111000 when 8|18|28|38|48|58 =10000000 when 9|19|29|39|49|59 =10011000=null; when 0|1|2|3|4|5|6|7|8|9 = ten when 20|21|22|23|24|25|26|27|28|29 = when 30|31|32|33|34|35|36|37|38|39 = when 40|41|42|43|44|45|46|47|48|49 = when 50|51|5

7、2|53|54|55|56|57|58|59 =entity i24bcd is-时显示architecture a of i24bcd is when 0|10|20 = when 1|11|21 = when 2|12|22 = when 3|13|23 = when 4|14 = when 5|15 = when 6|16 = when 7|17 = when 8|18 = when 9|19 = when 20|21|22|23 =回答者： ail傻大个 | 三级 | 2010-12-29 17:19 entity MINSECONDb isport（clk,clrm,stop:in

8、std_logic;-时钟/清零信号 secm1,secm0:out std_logic_vector（3 downto 0）;-秒高位/低位 co:out std_logic）;-输出/进位信号end MINSECONDb;architecture SEC of MINSECONDb issignal clk1,DOUT2:std_logic;process（clk,clrm）variable cnt1,cnt0:std_logic_vector（3 downto 0）;-计数 VARIABLE COUNT2 :INTEGER RANGE 0 TO 10 ;IF CLKEVENT AND C

9、LK=THEN IF COUNT2=0 AND COUNT210 THEN COUNT2:=COUNT2+1; ELSE COUNT2: DOUT2= NOT DOUT2; END IF;if clrm= then-当clr为1时，高低位均为0cnt1:0000cnt0:elsif clk if stop= cnt0:=cnt0;=cnt1;if cnt1=1001 and cnt0=1000 then-当记数为98（实际是经过59个记时脉冲）co-进位-低位为9elsif cnt0 then-小于9时=cnt0+1;-计数-elsif cnt0=-clk1=not clk1;elseif c

10、nt1 then-高位小于9时end if;secm1secm0end process;end SEC;秒模块程序清单entity SECOND isport（clk,clr: sec1,sec0:end SECOND;architecture SEC of SECOND isprocess（clk,clr）if clr= then-当ckr为1时，高低位均为00101 then-当记数为58（实际是经过59个记时脉冲） then-高位小于5时sec1sec0分模块程序清单 library ieee;entity MINUTE isport（clk,en: min1,min0:end MINU

11、TE;architecture MIN of MINUTE isprocess（clk）if clkif en=min1min0end MIN;时模块程序清单entity HOUR is-输入时钟/高电平有效的使能信号 h1,h0:out std_logic_vector（3 downto 0）;-时高位/低位end HOUR;architecture hour_arc of HOUR is-记数 then-上升沿触发 then-同时“使能”为100100011-高位/低位同时为0时 then-低位小于9时，低位记数累加-高位记数累加h1h0end hour_arc;动态扫描模块entity SELTIME is clk:-扫描时钟 secm1,secm0,sec1,sec0,min1,min0,h1,h0:in std_logic_vector（3 downto 0）;-分别为秒个位/时位；分个位/ daout:-输出 sel:out std_logic_vector（2 downto 0）;-位选信号end SELTIME;architecture fun of SELTIME is signal count:std_logic_vector（2 downto 0）;-计数信号 sel111 count000=count+1; case