VHDL数字钟代码Word文件下载.docx

VHDL数字钟代码Word文件下载.docx

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ten:

outstd_logic_vector（7downto0）;

one:

outstd_logic_vector（7downto0）

componenti24bcd

inintegerrange0to23;

signalcarry1,carry2:

signalabin1,abin2:

integerrange0to59;

signalabin3:

integerrange0to23;

signalclk_1h:

signalsh,sl,mh,ml,hh,hl:

std_logic_vector（7downto0）;

signalcnt:

integerrange0to5:

=0;

begin

process（clk）--分频为1hz

constantcounter_len:

integer:

=19999999;

variablecnt:

integerrange0tocounter_len;

begin

ifclk'

eventandclk='

1'

then

ifcnt=counter_lenthen

cnt:

else

=cnt+1;

endif;

casecntis

when0tocounter_len/2=>

clk_1h<

='

0'

;

whenothers=>

endcase;

endprocess;

process（clk）

variablecnt1:

integerrange0to200;

variablecnt2:

integerrange0to10;

ifcnt1=200then

cnt1:

ifcnt2=10then

cnt2:

if（cnt=5）then

cnt<

=cnt2+1;

=cnt1+1;

ifclk='

when0=>

duan<

="

000001"

data_o<

=sl;

when1=>

000010"

=sh;

when2=>

000100"

=ml;

when3=>

001000"

=mh;

when4=>

010000"

=hl;

when5=>

100000"

=hh;

whenothers=>

duan<

000000"

u1:

count60portmap（carry=>

clk_1h,rst=>

reset,times=>

abin1,full=>

carry1）;

u2:

carry1,rst=>

abin2,full=>

carry2）;

u3:

count24portmap（carry=>

carry2,rst=>

abin3）;

u4:

i60bcdportmap（interg=>

abin1,ten=>

sh,one=>

sl）;

u5:

abin2,ten=>

mh,one=>

ml）;

u6:

i24bcdportmap（interg=>

abin3,ten=>

hh,one=>

hl）;

entitycount60is--分，秒计数器

architectureaofcount60is

signaltime_s:

process（rst,carry）

ifrst='

time_s<

full<

elsifrising_edge（carry）then

iftime_s=59then

=time_s+1;

times<

=time_s;

libraryieee;

entitycount24is--时计数器

architectureaofcount24is

--full<

iftime_s=23then

entityi60bcdis--分，秒显示

architectureaofi60bcdis

process（interg）

caseintergis

when0|10|20|30|40|50=>

one<

11000000"

when1|11|21|31|41|51=>

11111001"

when2|12|22|32|42|52=>

10100100"

when3|13|23|33|43|53=>

10110000"

when4|14|24|34|44|54=>

10011001"

when5|15|25|35|45|55=>

10010010"

when6|16|26|36|46|56=>

10000011"

when7|17|27|37|47|57=>

11111000"

when8|18|28|38|48|58=>

10000000"

when9|19|29|39|49|59=>

10011000"

=null;

when0|1|2|3|4|5|6|7|8|9=>

ten<

when10|11|12|13|14|15|16|17|18|19=>

when20|21|22|23|24|25|26|27|28|29=>

when30|31|32|33|34|35|36|37|38|39=>

when40|41|42|43|44|45|46|47|48|49=>

when50|51|52|53|54|55|56|57|58|59=>

entityi24bcdis--时显示

architectureaofi24bcdis

when0|10|20=>

when1|11|21=>

when2|12|22=>

when3|13|23=>

when4|14=>

when5|15=>

when6|16=>

when7|17=>

when8|18=>

when9|19=>

when20|21|22|23=>

回答者：

ail傻大个|三级|2010-12-2917:

19

entityMINSECONDbis

port（clk,clrm,stop:

instd_logic;

----时钟/清零信号

secm1,secm0:

outstd_logic_vector（3downto0）;

----秒高位/低位

co:

outstd_logic）;

-------输出/进位信号

endMINSECONDb;

architectureSECofMINSECONDbis

signalclk1,DOUT2:

std_logic;

process（clk,clrm）

variablecnt1,cnt0:

std_logic_vector（3downto0）;

---计数

VARIABLECOUNT2:

INTEGERRANGE0TO10;

IFCLK'

EVENTANDCLK='

THEN

IFCOUNT2>

=0ANDCOUNT2<

10THEN

COUNT2:

=COUNT2+1;

ELSECOUNT2:

DOUT2<

=NOTDOUT2;

ENDIF;

ifclrm='

then----当clr为1时，高低位均为0

cnt1:

0000"

cnt0:

elsifclk'

ifstop='

cnt0:

=cnt0;

=cnt1;

ifcnt1="

1001"

andcnt0="

1000"

then----当记数为98（实际是经过59个记时脉冲）

co<

----进位

----低位为9

elsifcnt0<

"

then----小于9时

=cnt0+1;

----计数

--elsifcnt0="

--clk1<

=notclk1;

else

ifcnt1<

then----高位小于9时

endif;

secm1<

secm0<

endprocess;

endSEC;

秒模块程序清单

entitySECONDis

port（clk,clr:

sec1,sec0:

endSECOND;

architectureSECofSECONDis

process（clk,clr）

ifclr='

then----当ckr为1时，高低位均为0

0101"

then----当记数为58（实际是经过59个记时脉冲）

then----高位小于5时

sec1<

sec0<

分模块程序清单

libraryieee;

entityMINUTEis

port（clk,en:

min1,min0:

endMINUTE;

architectureMINofMINUTEis

process（clk）

ifclk'

ifen='

min1<

min0<

endMIN;

时模块程序清单

entityHOURis

----输入时钟/高电平有效的使能信号

h1,h0:

outstd_logic_vector（3downto0））;

----时高位/低位

endHOUR;

architecturehour_arcofHOURis

----记数

then---上升沿触发

then---同时“使能”为1

0010"

0011"

----高位/低位同时为0时

then----低位小于9时，低位记数累加

-----高位记数累加

h1<

h0<

endhour_arc;

动态扫描模块

entitySELTIMEis

clk:

------扫描时钟

secm1,secm0,sec1,sec0,min1,min0,h1,h0:

instd_logic_vector（3downto0）;

-----分别为秒个位/时位；

分个位/

daout:

----------------输出

sel:

outstd_logic_vector（2downto0））;

-----位选信号

endSELTIME;

architecturefunofSELTIMEis

signalcount:

std_logic_vector（2downto0）;

----计数信号

sel<

=count;

if（clk'

）then

if（count>

111"

count<

000"

=count+1;

case