数字时钟外文翻译.docx

1、数字时钟外文翻译资料范本 本资料为word版本，可以直接编辑和打印，感谢您的下载数字时钟外文翻译 地点：_时间：_说明：本资料适用于约定双方经过谈判，协商而共同承认，共同遵守的责任与义务，仅供参考，文档可直接下载或修改，不需要的部分可直接删除，使用时请详细阅读内容外文资料翻译L ED using digital tube digital display its high-brightness, indicating the advantages of intuitive intelligence is widely used in areas such as equipment and hou

2、sehold appliances. AT89C52This article describes a single-chip microcomputer as the core, to a total of anode high-brightness LED L ED as a display composed of seven figures show that the practical design of multi-function electronic clocks, the clock shows a week, hour, minute, second, it can be sw

3、itched to year, month, day showed that the whole point of music at the same time and from time to time the alarm time and other functions can also be used for electronic stopwatch.Clock circuit is the heart of the computer, which controls the rhythm of the work of the computer is through the complet

4、ion of complex sequential circuits function in different directions.Clock, since it was invented that day on, peoples lives has become an indispensable tool, especially in this era of efficient, the clock is in the human production and living, learning and other fields is widely. However, with the p

5、assage of time, people not only to the requirements of the clock is getting higher and higher precision, and functional requirements for the clock more and more, the clock has not only a tool used to display time, in many practical applications It also needs to be able to achieve more other function

6、s. Features such as alarm clock, calendar display, temperature measurement function, humidity measurements, voltage measurements, frequency measurements, have been under-voltage alarm function. Digital clocks to the peoples production and life has brought great convenience, but also greatly expands

7、the time feature the original clocks. Such as regular auto-alarm, Automatic time-ling, time process automation, from time to time broadcast, from closed-circuit automatic lights, oven timer switch, on-off power equipment, electrical and even a variety of timing is automatically enabled, all of which

8、 are based on digital clocks and watches based. It can be said that the design of the significance of multi-function Digital Clock Digital Clock is not just itself, a greater significance of the multi-function digital clock in a number of real-time control systems. In many practical applications, as

9、 long as the digital clock circuit of the programs and hardware to a certain degree of modification could be useful for real-time control system, which applied to the actual work and production to. Thus, digital clock and to expand its applications, has a very practical significance.With the develop

10、ment of human civilization, science and technology, there is the request of the clock continues to improve. Clock has not only seen as a tool to display the time, in many practical applications also need to be able to achieve more other functions. High-precision, multifunction, small size, low power

11、 consumption, is the development trend of the modern clock. In this trend, digital clock, multifunction clock has become the modern design of the production of research-led direction. This article is based on this design direction for the control of a single-chip core design requirements of a multi-

12、function indicators in line with the digital clock.The design is based on the principle of single-chip technology to chip AT89C52single-chip microcomputer as the core controller, through the production of hardware and software procedures for the preparation, design to produce a multi-functional digi

13、tal clock system. The clock system mainly by clock module, alarm module, the ambient temperature detection module, liquid crystal display module, control module and the keyboard signal prompted module. System is simple and clear user interface that can 4V 7V DC power under normal operation. Able to

14、accurately display time (display format hh: mm: seconds seconds, 24-hour system), may be time to adjust at any time, with clock time settings, alarm on / off, only to make functions, where the clock to measure the ambient temperature and displayed. Hardware and software design into the guiding ideol

15、ogy, give full play to the single-chip features, most of the functions through software programming to achieve, the circuit is simple and clear, high system stability. At the same time, the clock system also has the power of small, low cost, and highly practical. System components as a result of les

16、s use, single-chip occupied by the I / O port not more than, the system has a certain degree of scalability.Clock design is no theory of discrete logic, programmable logic, or using full-custom silicon devices of any digital design, in order to successfully operate and reliable clock is crucial. Poo

17、r design of the clock in the limits of temperature, voltage deviation or the manufacturing process will result in the case wrong, and debugging difficult, spending a lot. In the design of FPGA / CPLD clock when several types of commonly used. Clock can be divided into the following four types: globa

18、l clock, clock gating, multi-level logic clock clock and volatility. Multi-clock system to include the above-mentioned four types of any combination of the clock.No matter what methods are the real circuit clock tree can not achieve the ideal assumption that the clock, so we must be based on an idea

19、l clock, the clock real work to build a model to analyze the circuit, so as to make the circuit performance and the practical work as expected . Clock in the actual model, we have to consider the spread of clock-tree skew, vertical jump and absolute bias and other uncertainties.To register, the cloc

20、k was working along the arrival of the data terminal when it should have been stable, so as to ensure that the work along the sampling clock to the accuracy of the data, this data preparation time that we call set-up time (setup time). Data should also be working along the clock to maintain over a p

21、eriod of time, this period of time known as the hold time (hold time).Global clock for a design project, the global clock (or clock synchronous) is the simplest and most predictable clock. In the PLD / FPGA design of the clock the best options are: by a dedicated global clock input pins of a single

22、master clock-driven clock design projects to each flip-flop. As long as possible should be used in the design of global clock projects. PLD / FPGA has a dedicated global clock pins, the device is directly connected to each register. Global clock to provide such a device in the shortest possible dela

23、y to the output clock.Clock-gated in many applications, the entire design of the overall use of external clock is not possible or practical. With the product of PLD logic array clock (that is, the clock is generated by the logic), to allow arbitrary function alone all trigger clock. However, when yo

24、u use the array clock, the clock should be carefully analyzed the function, in order to avoid glitches.Usually constitute the array clock clock-gated. Clock gating often interface with the microprocessor, and used the address to write to control the pulse line. However, when using combination of fli

25、p-flop when the clock function, usually there is a clock-gated. If the following conditions, such as clock gating can be as reliable as global clock work:Drive the clock logic must contain only one and the door or a or gate. If any additional work in some state of logic, the competition will be the

26、burr.A logic gate input as the actual clock, and the logic gate must be of all other input as the address or control lines, in relation to their compliance with the establishment and maintenance of clock time bound.Multi-level logic generated clock when the clock-gating logic of the combination of m

27、ore than one (or more than the individual and doors or or gate), the evidence of the reliability of the design of the project has become very difficult. Even if the prototype or simulation results show that there is no static dangerous, but in fact the risk may still exist. In general, we should not

28、 use multi-level combinational logic to clock the flip-flop in the PLD design.Traveling-wave clock clock another popular use of traveling-wave circuit is the clock, that is, the output of a flip-flop used as a clock input of another flip-flop. If careful design, traveling-wave clock can be the same

29、as the global clock to work reliably. However, the traveling-wave clock made from time to time with the calculation of the circuit becomes very complicated. Line-wave traveling-wave clock flip-flop of the chain have a greater clock time between the offset and exceed the worst case the set-up time, h

30、old time and clock to the output circuit of the delay, allowing the system to the actual slowed down.Multi-clock system, many system requirements within the same multi-PLD clock. The most common example is the two asynchronous interfaces between microprocessors, or microprocessors and asynchronous c

31、ommunication channel interface. As the clock signal between the two requirements to establish and maintain a certain time, so that the above application from time to time the introduction of additional constraints. They also requested that some asynchronous synchronization signal.In many application

32、s, only the synchronization of asynchronous signals is not enough, when the system of two or more non-homologous clock, the data it is difficult to establish and maintain the time to be assured that we will face the complex matter of time . The best way is to all non-homologous clock synchronization. PLD internal use of the lock loop (PLL or DLL) is a very good, but not all of PLD with a PLL, DLL, and chip PLL with most expensive, so unless there are special requirements, the general occasions PLL can not use with the PLD.At this time we need to take to enable the use of the D flip-fl