XPS程序分析Word格式.docx

1、 PORT userio_hexdisp_right = userio_hexdisp_right, DIR = O, VEC = 6: PORT userio_hexdisp_left_dp = userio_hexdisp_left_dp, DIR = O PORT userio_hexdisp_right_dp = userio_hexdisp_right_dp, DIR = O PORT userio_rfa_led_red = userio_rfa_led_red, DIR = O PORT userio_rfa_led_green = userio_rfa_led_green, D

2、IR = O PORT userio_rfb_led_red = userio_rfb_led_red, DIR = O PORT userio_rfb_led_green = userio_rfb_led_green, DIR = O# Ethernet pins PORT ETH_COMA = net_gnd, DIR = O# ETH_A PORT ETH_A_PHY_RST_N = ETH_A_PHY_RST_N, DIR = O PORT ETH_A_MDIO = ETH_A_MDIO, DIR = IO PORT ETH_A_MDC = ETH_A_MDC, DIR = O POR

3、T ETH_A_RGMII_TXC = ETH_A_RGMII_TXC, DIR = O PORT ETH_A_RGMII_TX_CTL = ETH_A_RGMII_TX_CTL, DIR = O PORT ETH_A_RGMII_TXD = ETH_A_RGMII_TXD, DIR = O, VEC = 3: PORT ETH_A_RGMII_RXC = ETH_A_RGMII_RXC, DIR = I PORT ETH_A_RGMII_RX_CTL = ETH_A_RGMII_RX_CTL, DIR = I PORT ETH_A_RGMII_RXD = ETH_A_RGMII_RXD, D

4、IR = I, VEC = 3: PORT ETH_A_PD = net_gnd, DIR = O# ETH_B PORT ETH_B_MDIO = ETH_B_MDIO, DIR = IO PORT ETH_B_MDC = ETH_B_MDC, DIR = O PORT ETH_B_RGMII_TXC = ETH_B_RGMII_TXC, DIR = O PORT ETH_B_RGMII_TX_CTL = ETH_B_RGMII_TX_CTL, DIR = O PORT ETH_B_RGMII_TXD = ETH_B_RGMII_TXD, DIR = O, VEC = 3: PORT ETH

5、_B_RGMII_RXC = ETH_B_RGMII_RXC, DIR = I PORT ETH_B_RGMII_RX_CTL = ETH_B_RGMII_RX_CTL, DIR = I PORT ETH_B_RGMII_RXD = ETH_B_RGMII_RXD, DIR = I, VEC = 3: PORT ETH_B_PD = net_gnd, DIR = O# USB UART PORT usb_uart_rx = usb_uart_rx, DIR = I PORT usb_uart_tx = usb_uart_tx, DIR = O# AD9512 clock buffer cont

6、rol pins （RF reference & sampling clocks） PORT clk_rfref_spi_cs_n_pin = clk_rfref_spi_cs_n, DIR = O PORT clk_rfref_spi_mosi_pin = clk_rfref_spi_mosi, DIR = O PORT clk_rfref_spi_sclk_pin = clk_rfref_spi_sclk, DIR = O PORT clk_rfref_spi_miso_pin = clk_rfref_spi_miso, DIR = I PORT clk_rfref_func_pin =

7、net_vcc, DIR = O PORT clk_samp_spi_cs_n_pin = clk_samp_spi_cs_n, DIR = O PORT clk_samp_spi_mosi_pin = clk_samp_spi_mosi, DIR = O PORT clk_samp_spi_sclk_pin = clk_samp_spi_sclk, DIR = O PORT clk_samp_spi_miso_pin = clk_samp_spi_miso, DIR = I PORT clk_samp_func_pin = net_vcc, DIR = O# IIC EEPROM pins

8、on-board PORT iic_eeprom_onboard_scl_pin = iic_eeprom_onboard_scl_pin, DIR = IO PORT iic_eeprom_onboard_sda_pin = iic_eeprom_onboard_sda_pin, DIR = IO# Switches on CM-MMCX for clock src selection （ok if CM-MMCX is not installed） PORT cm_mmcx_sw = cm_mmcx_sw, DIR = I, VEC = 0:1# 80MHz sampling clock

9、from AD9512 PORT samp_clk_p_pin = ad_refclk_in, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 80000000 PORT samp_clk_n_pin = ad_refclk_in, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 80000000# 200MHz LVDS oscillator input PORT osc200_p_pin = osc200_in, DIR = I, DIFFEREN

10、TIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000 PORT osc200_n_pin = osc200_in, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000# AD9963 ADC/DAC control pins （RFA & RFB） PORT RFA_AD_spi_cs_n_pin = RFA_AD_spi_cs_n, DIR = O PORT RFA_AD_spi_sdio = RFA_AD_spi_sdio, DIR = IO PORT

11、 RFA_AD_spi_sclk_pin = RFA_AD_spi_sclk, DIR = O PORT RFA_AD_reset_n_pin = RFA_AD_reset_n, DIR = O PORT RFB_AD_spi_cs_n_pin = RFB_AD_spi_cs_n, DIR = O PORT RFB_AD_spi_sdio = RFB_AD_spi_sdio, DIR = IO PORT RFB_AD_spi_sclk_pin = RFB_AD_spi_sclk, DIR = O PORT RFB_AD_reset_n_pin = RFB_AD_reset_n, DIR = O

12、# RFA AD pins PORT RFA_AD_TRXD = rfa_trxd, DIR = I, VEC = 11: PORT RFA_AD_TRXCLK = rfa_trxclk, DIR = I PORT RFA_AD_TRXIQ = rfa_trxiq, DIR = I PORT RFA_AD_TXD = rfa_txd, DIR = O, VEC = 11: PORT RFA_AD_TXIQ = rfa_txiq, DIR = O PORT RFA_AD_TXCLK = rfa_txclk, DIR = O# RFB AD pins PORT RFB_AD_TRXD = rfb_

13、trxd, DIR = I, VEC = 11: PORT RFB_AD_TRXCLK = rfb_trxclk, DIR = I PORT RFB_AD_TRXIQ = rfb_trxiq, DIR = I PORT RFB_AD_TXD = rfb_txd, DIR = O, VEC = 11: PORT RFB_AD_TXIQ = rfb_txiq, DIR = O PORT RFB_AD_TXCLK = rfb_txclk, DIR = O# RSSI ADC pins PORT RFA_RSSI_D = RFA_RSSI_D, DIR = I, VEC = 9: PORT RFB_R

14、SSI_D = RFB_RSSI_D, DIR = I, VEC = 9: PORT RF_RSSI_CLK = wlan_rssi_clk, DIR = O PORT RF_RSSI_PD = net_gnd, DIR = O# RFA transceiver and front-end PORT RFA_TxEn_pin = RFA_TxEn, DIR = O PORT RFA_RxEn_pin = RFA_RxEn, DIR = O PORT RFA_RxHP_pin = RFA_RxHP, DIR = O PORT RFA_SHDN_pin = RFA_SHDN, DIR = O PO

15、RT RFA_SPI_SCLK_pin = RFA_SPI_SCLK, DIR = O PORT RFA_SPI_MOSI_pin = RFA_SPI_MOSI, DIR = O PORT RFA_SPI_CSn_pin = RFA_SPI_CSn, DIR = O PORT RFA_B_pin = RFA_B, DIR = O, VEC = 0:6 PORT RFA_LD_pin = RFA_LD, DIR = I PORT RFA_PAEn_24_pin = RFA_PAEn_24, DIR = O PORT RFA_PAEn_5_pin = RFA_PAEn_5, DIR = O POR

16、T RFA_AntSw_pin = RFA_AntSw, DIR = O, VEC = 0:# RFB transceiver and front-end PORT RFB_TxEn_pin = RFB_TxEn, DIR = O PORT RFB_RxEn_pin = RFB_RxEn, DIR = O PORT RFB_RxHP_pin = RFB_RxHP, DIR = O PORT RFB_SHDN_pin = RFB_SHDN, DIR = O PORT RFB_SPI_SCLK_pin = RFB_SPI_SCLK, DIR = O PORT RFB_SPI_MOSI_pin =

17、RFB_SPI_MOSI, DIR = O PORT RFB_SPI_CSn_pin = RFB_SPI_CSn, DIR = O PORT RFB_B_pin = RFB_B, DIR = O, VEC = 0: PORT RFB_LD_pin = RFB_LD, DIR = I PORT RFB_PAEn_24_pin = RFB_PAEn_24, DIR = O PORT RFB_PAEn_5_pin = RFB_PAEn_5, DIR = O PORT RFB_AntSw_pin = RFB_AntSw, DIR = O, VEC = 0:# DDR3 SODIMM PORT ddr3

18、_sodimm_ck_p = ddr3_sodimm_ck_p, DIR = O, SIGIS = CLK, VEC = 1: PORT ddr3_sodimm_ck_n = ddr3_sodimm_ck_n, DIR = O, SIGIS = CLK, VEC = 1: PORT ddr3_sodimm_cke = ddr3_sodimm_cke, DIR = O PORT ddr3_sodimm_cs_n = ddr3_sodimm_cs_n, DIR = O PORT ddr3_sodimm_odt = ddr3_sodimm_odt, DIR = O PORT ddr3_sodimm_

19、ras_n = ddr3_sodimm_ras_n, DIR = O PORT ddr3_sodimm_cas_n = ddr3_sodimm_cas_n, DIR = O PORT ddr3_sodimm_we_n = ddr3_sodimm_we_n, DIR = O PORT ddr3_sodimm_ba = ddr3_sodimm_ba, DIR = O, VEC = 2: PORT ddr3_sodimm_addr = ddr3_sodimm_addr, DIR = O, VEC = 14: PORT ddr3_sodimm_dq = ddr3_sodimm_dq, DIR = IO

20、, VEC = 63: PORT ddr3_sodimm_dm = ddr3_sodimm_dm, DIR = O, VEC = 7: PORT ddr3_sodimm_reset_n = ddr3_sodimm_reset_n, DIR = O PORT ddr3_sodimm_dqs_p = ddr3_sodimm_dqs_p, DIR = IO, VEC = 7: PORT ddr3_sodimm_dqs_n = ddr3_sodimm_dqs_n, DIR = IO, VEC = 7:# Debug pins PORT debughdr = dbg_gpio_b2 & dbg_gpio

21、_b1 & dbg_gpio_b0 & mac_nav_active & mac_backoff_active & mac_idle_for_difs & dbg_mpdu_tx_pending & dbg_rssi_det & mac_phy_rx_fcs_good_ind & dbg_lts_timeout & dbg_pkt_det_dsss & dbg_pkt_det_ofdm & dbg_dsss_rx_active & dbg_ofdm_rx_active & dbg_tx_running, DIR = O, VEC = 14: PORT wlan_phy_rx_pkt_det_i

22、n_pin = net_wlan_phy_rx_pkt_det_in_pin, DIR = IBEGIN wlan_phy_tx_pmd_axiw PARAMETER INSTANCE = wlan_phy_tx PARAMETER HW_VER = 2.01.c PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 7 PARAMETER C_INTERCONNECT_S_

23、AXI_R_REGISTER = 7 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7 PARAMETER C_BASEADDR = 0x78e00000 PARAMETER C_HIGHADDR = 0x78e0ffff BUS_INTERFACE PORTB = WLAN_TX_PKT_BUF_PORTB BUS_INTERFACE S_AXI = mb_low_axi_periph PORT axi_aclk = clk_160MHz PORT sysgen_clk = clk_160MHz PORT dac_tx_clk = clk_20MHz

24、 PORT rfa_dac_i = RFA_TX_I PORT rfa_dac_q = RFA_TX_Q PORT rfb_dac_i = RFB_TX_I PORT rfb_dac_q = RFB_TX_Q PORT rx_sigs_invalid = rx_sigs_invalid# RC - PHY start PORT RC_PHY_START = tx_phy_start# PHY - RC state ctrl PORT rc_usr_rxen = rc_usr_rxen PORT rc_usr_txen_a = phy_rc_txen_a PORT rc_usr_txen_b =

25、 phy_rc_txen_b PORT rc_tx_gain_a = phy_rc_tx_gain_a PORT rc_tx_gain_b = phy_rc_tx_gain_b# MAC Tx PHY ports PORT phy_tx_gain_a = mac_phy_tx_gain_a PORT phy_tx_gain_b = mac_phy_tx_gain_b PORT phy_tx_pkt_buf = mac_phy_tx_pkt_buf PORT phy_tx_start = mac_phy_tx_start PORT phy_tx_done = mac_phy_tx_done PO

26、RT phy_tx_started = mac_phy_tx_started PORT phy_tx_ant_mask = mac_phy_tx_ant_mask PORT mac_timestamp_lsb = mac_tx_start_timestamp_lsb PORT mac_timestamp_msb = mac_tx_start_timestamp_msb# Debug ports PORT dbg_tx_running = dbg_tx_runningENDBEGIN wlan_phy_rx_pmd_axiw PARAMETER INSTANCE = wlan_phy_rx PA

27、RAMETER HW_VER = 2.04.i PARAMETER C_BASEADDR = 0x78e20000 PARAMETER C_HIGHADDR = 0x78e2ffff BUS_INTERFACE PORTB = WLAN_RX_PKT_BUF_PORTB PORT pkt_det_in = net_wlan_phy_rx_pkt_det_in_pin PORT adc_rx_clk = agc_iq_valid_out PORT rfa_rx_i = agc_rfa_i PORT rfa_rx_q = agc_rfa_q PORT rfa_rssi = RFA_RSSI_D PORT rfb_rx_i = agc_rfb_i PORT rfb_rx_q = agc_rfb_q PORT rfb_rssi = RFB_RSSI_D PORT rssi_adc_clk = wlan_rssi_clk PORT pkt_det_o = phy_rx_pkt_det PORT rfa_g_rf = agc_rfa_g_rf PORT rfa_g_bb = agc_rfa_g_bb PORT rfb_g_rf = agc_rfb_g_rf PORT rf