EDA技术实验内容交通灯74ls138与门等.docx

1、EDA技术实验内容交通灯74ls138与门等1与门library ieee;use ieee.std_logic_1164.all;entity and is port(a,b:in std_logic;y:out std_logic);end;architecture ab of and isbeginy=a and b;end;2.74LS138译码器library ieee;use ieee.std_logic_1164.all;entity 74LS138 is port(a,b,c:in std_logic; y:out std_logic_vector(7 downto 0);en

2、d;architecture art of 74LS138 issignal data:std_logic_vector(2 downto 0);begindatayyyyyyyynull; end case;end art;3计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY COUNT ISPORT ( CLK,RST,EN : IN STD_LOGIC ; CO: OUT STD_LOGIC; CQ: OUT STD_LOGIC_VECTOR (3DOWNTO 0);END COUNT;ARCHITECTURE ONE OF COUNT

3、ISBEGINPROCESS (CLK,RST,EN)VARIABLE CQ1:STD_LOGIC_VECTOR(3 DOWN TO 0);BEGINIF RST=1 THEN CQ1:=(OTHERS=0);ELSIF CLKEVENT AND CLK=1 THEN IF EN=1THEN IF CQ10) END IF;END IF;IF CQ1=15 THEN CO=1;ELSE CO=0;END IF;CQ BT = 00000001 ; A BT = 00000010 ; A BT = 00000100 ; A BT = 00001000 ; A BT = 00010000 ; A

4、BT = 00100000 ; A BT = 01000000 ; A BT = 10000000 ; A NULL ; END CASE ; END PROCESS P1; P2：PROCESS(CLK) BEGIN IF CLKEVENT AND CLK = 1 THEN CNT8 SG SG SG SG SG SG SG SG SG SG SG SG SG SG SG SG NULL ; END CASE ; END PROCESS P3; 5.正弦信号发生器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY sin IS PORT(clk:I

5、N STD_LOGIC; DOUT:OUT INTEGER RANGE 255 DOWNTO 0);END ENTITY sin;ARCHITECTURE behave OF sin IS SIGNAL Q:INTEGER RANGE 63 DOWNTO 0;BEGIN PROCESS(clk) BEGIN IF(CLKEVENT AND clk=1)THEN QDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTD

6、OUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTNULL; END CASE; END PROCESS;END ARCHITECTURE behave;6.A/D采样控制电路ADC0809LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY adc0809 IS PORT ( ina : IN STD_LOGIC_VECTOR

7、(7 DOWNTO 0); -0809的8位转换数据输出 CLK ,EOC : IN STD_LOGIC; -CLK xitong工作时钟 ALE, ck, OE : OUT STD_LOGIC; -ck是0809de 工作时钟adda,addb,addc:out std_logic; outa : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);END adc0809 ;ARCHITECTURE behav OF adc0809 IS signal fp:std_logic_vector(3 downto 0); signal f:std_logic;TYPE state

8、s IS (st0,st2,st3,st4,st5,st6) ; -定义各状态子类型 SIGNAL current_state, next_state: states :=st0 ; SIGNAL REGL : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL LOCK : STD_LOGIC; - 转换后数据输出锁存时钟信号 BEGIN ADDA = 0;addb=0;addc=0; process( CLK) begin if( CLKevent and CLK=1)then if fp=1100 then fp=0000; f=not f; else fp=fp+

9、1; end if; end if; end process; ck ALE=0;OE=0;LOCK=0 ;next_state ALE=1;OE=0;LOCK=0 ;next_state ALE=0;OE=0;LOCK=0; IF (EOC=1) THEN next_state = st3; -测试EOC的下降沿 ELSE next_state ALE=0;OE=0;LOCK=0; IF (EOC=0) THEN next_state = st4; -测试EOC的上升沿，=1表明转换结束 ELSE next_state ALE=0;OE=1;LOCK=0;next_state ALE=0;O

10、E=1;LOCK=1;next_state ALE=0;OE=0;LOCK=0;next_state = st0; END CASE ; END PROCESS PRO ; PROCESS (f) BEGIN IF ( fEVENT AND f=1) THEN current_state = next_state; - 在时钟上升沿，转换至下一状态 END IF; END PROCESS; - 由信号current_state将当前状态值带出此进程，进入进程PRO PROCESS (LOCK) - 此进程中，在LOCK的上升沿，将转换好的数据锁入 BEGIN IF LOCK=1 AND LOC

11、KEVENT THEN REGL = ina ; END IF; END PROCESS ; with REGL(3 downto 0) selectouta(6 downto 0) =0110000when0001,-1 1101101when0010,-2 1111001when0011,-3 0110011when0100,-4 1011011when0101,-5 1011111when0110,-6 1110000when0111,-7 1111111when1000,-8 1111011when1001,-9 1110111when1010,-A 0011111when1011,-

12、b 1001110when1100,-c 0111101when1101,-d 1001111when1110,-e 1000111when1111,-f 1111110when others;-0with REGL(7 downto 4) selectouta(13 downto 7) =0110000when0001,-1 1101101when0010,-2 1111001when0011,-3 0110011when0100,-4 1011011when0101,-5 1011111when0110,-6 1110000when0111,-7 1111111when1000,-8 11

13、11011when1001,-9 1110111when1010,-A 0011111when1011,-b 1001110when1100,-c 0111101when1101,-d 1001111when1110,-e 1000111when1111,-f 1111110when others;-0END behav;7.交通灯控制器计数器的程序Library Ieee;Use Ieee.Std_Logic_1164.All;Entity Counter IsPort(Clock:In Std_Logic; Reset:In Std_Logic; Hold:In Std_Logic; Co

14、untnum: Buffer Integer Range 0 To 49);End;Architecture Behavior Of Counter IsBegin Process(Reset,Clock) Begin If Reset=1 Then Countnum=0; Elsif Rising_Edge(Clock) ThenIf Hold=1 Then 当出现紧急情况时，计数器暂停计数Countnum=Countnum;Else If Countnum=49 Then Countnum=0; Else Countnum=Countnum+1;End If;End If; End If;

15、 End Process;End;1控制器的程序Library Ieee;Use Ieee.Std_Logic_1164.All;Entity Controller IsPort(Clock:In Std_Logic; Hold:In Std_Logic; Countnum:In Integer Range 0 To 49; 前级计数器的计数值 Numa,Numb:Out Integer Range 0 To 25; 倒计时数值的计数值 Reda,Greena,Yellowa:Out Std_Logic; 控制东西方向红黄绿灯的亮灭 Redb,Greenb,Yellowb:Out Std_Lo

16、gic; 控制南北方向红黄绿灯的亮灭 Flash:Out Std_Logic); 用以指示七段数码管显示数字的闪烁End;Architecture Behavior Of Controller IsBegin Process(Clock) BeginIf Falling_Edge (Clock) Then 计数器是上升沿改变计数值，此处下降沿读取 If Hold=1 Then Reda=1; Redb=1; Greena=0; Greenb=0; Yellowa=0; Yellowb=0; Flash=1; Else Flash=0; If Countnum=19 Then Numa=20-C

17、ountnum; 计数器东西方向倒计时 Reda=0; Greena=1; Yellowa=0; Elsif (Countnum=24) Then Numa=25-Countnum; Reda=0; Greena=0; Yellowa=1; Else Numa=50-Countnum; Reda=1; Greena=0; Yellowa=0; End If;If Countnum=24 Then 计数器南北方向倒计时 Numb=25-Countnum; Redb=1; Greenb=0; Yellowb=0;Elsif Countnum=44 Then Numb=45-Countnum; Re

18、db=0; Greenb=1; Yellowb=0;Else Numb=50-Countnum; Redb=0; Greenb=0; Yellowb=20 Then Numa=2; Numb=10 Then Numa=1; Numb=Numin-10; Else Numa=0; Numb=Numin; End If; End Process;End;.4.1七段译码电路的程序Library Ieee;Use Ieee.Std_Logic_1164.All;Entity Displayone IsPort(Clock: In Std_Logic;Flash: In Std_Logic;Qin:

19、In Std_Logic_Vector(3 Downto 0);Display: Out Std_Logic_Vector(0 To 6);End;Architecture Decoder Of Displayone IsSignal Timeout:Integer Range 0 To 63;Begin Process(Clock) Begin If Rising_Edge(Clock) Then If Flash=0 Then Timeout=0; Else If Timeout=63 Then Timeout=0; Else Timeout=Timeout + 1; End If; End If; If TimeoutDisplay=0111111; When0001=