EDA技术实验内容交通灯74ls138与门等.docx
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EDA技术实验内容交通灯74ls138与门等
1．与门
libraryieee;
useieee.std_logic_1164.all;
entityandis
port（a,b:
instd_logic;
y:
outstd_logic）;
end;
architectureabofandis
begin
y<=aandb;
end;
2.74LS138译码器
libraryieee;
useieee.std_logic_1164.all;
entity74LS138is
port（a,b,c:
instd_logic;
y:
outstd_logic_vector（7downto0））;
end;
architectureartof74LS138is
signaldata:
std_logic_vector（2downto0）;
begin
data<=c&b&a;
casedatais
when"000"=>y<="11111110";
when"001"=>y<="11111101";
when"010"=>y<="11111011";
when"011"=>y<="11110111";
when"100"=>y<="11101111";
when"101"=>y<="11011111";
when"110"=>y<="10111111";
when"111"=>y<="01111111";
whenothers=>null;
endcase;
endart;
3．计数器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYCOUNTIS
PORT（CLK,RST,EN:
INSTD_LOGIC;
CO:
OUTSTD_LOGIC;
CQ:
OUTSTD_LOGIC_VECTOR（3DOWNTO0））;
ENDCOUNT;
ARCHITECTUREONEOFCOUNTIS
BEGIN
PROCESS（CLK,RST,EN）
VARIABLECQ1:
STD_LOGIC_VECTOR（3DOWNTO0）;
BEGIN
IFRST=‘1’THENCQ1:
=（OTHERS=>‘0’）;
ELSIFCLK’EVENTANDCLK=‘1’THEN
IFEN=‘1’THEN
IFCQ1<15THENCQ1:
=CQ1+1;
ELSECQ1:
=（OTHERS=>‘0’）
ENDIF;
ENDIF;
IFCQ1=15THENCO<=‘1’;
ELSECO<=‘0’;
ENDIF;
CQ<=CQ1;
ENDPROCESS;
ENDONE;
4扫描显示电路设计
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYSCAN_LEDIS
PORT（CLK:
INSTD_LOGIC;
SG:
OUTSTD_LOGIC_VECTOR（6DOWNTO0）;--段控制信号输出
BT:
OUTSTD_LOGIC_VECTOR（7DOWNTO0））;--位控制信号输出
END;
ARCHITECTUREoneOFSCAN_LEDIS
SIGNALCNT8:
STD_LOGIC_VECTOR（2DOWNTO0）;
SIGNALA:
INTEGERRANGE0TO15;
BEGIN
P1：
PROCESS（CNT8）
BEGIN
CASECNT8IS
WHEN"000"=>BT<="00000001";A<=1;
WHEN"001"=>BT<="00000010";A<=3;
WHEN"010"=>BT<="00000100";A<=5;
WHEN"011"=>BT<="00001000";A<=7;
WHEN"100"=>BT<="00010000";A<=9;
WHEN"101"=>BT<="00100000";A<=11;
WHEN"110"=>BT<="01000000";A<=13;
WHEN"111"=>BT<="10000000";A<=15;
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESSP1;
P2：
PROCESS（CLK）
BEGIN
IFCLK'EVENTANDCLK='1'THENCNT8<=CNT8+1;
ENDIF;
ENDPROCESSP2;
P3：
PROCESS（A）–-译码电路
BEGIN
CASEAIS
WHEN0=>SG<="0111111";WHEN1=>SG<="0000110";
WHEN2=>SG<="1011011";WHEN3=>SG<="1001111";
WHEN4=>SG<="1100110";WHEN5=>SG<="1101101";
WHEN6=>SG<="1111101";WHEN7=>SG<="0000111";
WHEN8=>SG<="1111111";WHEN9=>SG<="1101111";
WHEN10=>SG<="1110111";WHEN11=>SG<="1111100";
WHEN12=>SG<="0111001";WHEN13=>SG<="1011110";
WHEN14=>SG<="1111001";WHEN15=>SG<="1110001";
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESSP3;
5.正弦信号发生器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYsinIS
PORT（clk:
INSTD_LOGIC;
DOUT:
OUTINTEGERRANGE255DOWNTO0）;
ENDENTITYsin;
ARCHITECTUREbehaveOFsinIS
SIGNALQ:
INTEGERRANGE63DOWNTO0;
BEGIN
PROCESS（clk）
BEGIN
IF（CLK'EVENTANDclk='1'）THEN
Q<=Q+1;
ENDIF;
ENDPROCESS;
PROCESS（Q）
BEGIN
CASEQIS
WHEN00=>DOUT<=255;WHEN01=>DOUT<=254;
WHEN02=>DOUT<=252;WHEN03=>DOUT<=249;
WHEN04=>DOUT<=245;WHEN05=>DOUT<=239;
WHEN06=>DOUT<=233;WHEN07=>DOUT<=225;
WHEN08=>DOUT<=217;WHEN09=>DOUT<=207;
WHEN10=>DOUT<=197;WHEN11=>DOUT<=186;
WHEN12=>DOUT<=174;WHEN13=>DOUT<=162;
WHEN14=>DOUT<=150;WHEN15=>DOUT<=137;
WHEN16=>DOUT<=124;WHEN17=>DOUT<=112;
WHEN18=>DOUT<=99;WHEN19=>DOUT<=87;
WHEN20=>DOUT<=75;WHEN21=>DOUT<=64;
WHEN22=>DOUT<=53;WHEN23=>DOUT<=43;
WHEN24=>DOUT<=34;WHEN25=>DOUT<=26;
WHEN26=>DOUT<=19;WHEN27=>DOUT<=13;
WHEN28=>DOUT<=8;WHEN29=>DOUT<=4;
WHEN30=>DOUT<=1;WHEN31=>DOUT<=0;
WHEN32=>DOUT<=0;WHEN33=>DOUT<=1;
WHEN34=>DOUT<=4;WHEN35=>DOUT<=8;
WHEN36=>DOUT<=13;WHEN37=>DOUT<=19;
WHEN38=>DOUT<=26;WHEN39=>DOUT<=24;
WHEN40=>DOUT<=43;WHEN41=>DOUT<=53;
WHEN42=>DOUT<=64;WHEN43=>DOUT<=75;
WHEN44=>DOUT<=87;WHEN45=>DOUT<=99;
WHEN46=>DOUT<=112;WHEN47=>DOUT<=124;
WHEN48=>DOUT<=137;WHEN49=>DOUT<=150;
WHEN50=>DOUT<=162;WHEN51=>DOUT<=174;
WHEN52=>DOUT<=186;WHEN53=>DOUT<=197;
WHEN54=>DOUT<=207;WHEN55=>DOUT<=217;
WHEN56=>DOUT<=225;WHEN57=>DOUT<=233;
WHEN58=>DOUT<=239;WHEN59=>DOUT<=245;
WHEN60=>DOUT<=249;WHEN61=>DOUT<=252;
WHEN62=>DOUT<=254;WHEN63=>DOUT<=255;
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
ENDARCHITECTUREbehave;
6.A/D采样控制电路ADC0809
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYadc0809IS
PORT（ina:
INSTD_LOGIC_VECTOR（7DOWNTO0）;--0809的8位转换数据输出
CLK,EOC:
INSTD_LOGIC;--CLKxitong工作时钟
ALE,ck,OE:
OUTSTD_LOGIC;--ck是0809de工作时钟
adda,addb,addc:
outstd_logic;
outa:
OUTSTD_LOGIC_VECTOR（13DOWNTO0））;
ENDadc0809;
ARCHITECTUREbehavOFadc0809IS
signalfp:
std_logic_vector（3downto0）;
signalf:
std_logic;
TYPEstatesIS（st0,st2,st3,st4,st5,st6）;--定义各状态子类型
SIGNALcurrent_state,next_state:
states:
=st0;
SIGNALREGL:
STD_LOGIC_VECTOR（7DOWNTO0）;
SIGNALLOCK:
STD_LOGIC;--转换后数据输出锁存时钟信号
BEGIN
ADDA<='0';addb<='0';addc<='0';
process（CLK）
begin
if（CLK'eventandCLK='1'）then
iffp="1100"then
fp<="0000";
f<=notf;
else
fp<=fp+1;
endif;
endif;
endprocess;
ck<=f;
PRO:
PROCESS（current_state,EOC）BEGIN--规定各状态转换方式
CASEcurrent_stateIS
WHENst0=>ALE<='0';OE<='0';LOCK<='0';next_state<=st2;
WHENst2=>ALE<='1';OE<='0';LOCK<='0';next_state<=st3;
WHENst3=>ALE<='0';OE<='0';LOCK<='0';
IF（EOC='1'）THENnext_state<=st3;--测试EOC的下降沿
ELSEnext_state<=st4;
ENDIF;
WHENst4=>ALE<='0';OE<='0';LOCK<='0';
IF（EOC='0'）THENnext_state<=st4;--测试EOC的上升沿，=1表明转换结束
ELSEnext_state<=st5;--继续等待
ENDIF;
WHENst5=>ALE<='0';OE<='1';LOCK<='0';next_state<=st6;
WHENst6=>ALE<='0';OE<='1';LOCK<='1';next_state<=st0;
WHENOTHERS=>ALE<='0';OE<='0';LOCK<='0';next_state<=st0;
ENDCASE;
ENDPROCESSPRO;
PROCESS（f）
BEGIN
IF（f'EVENTANDf='1'）THEN
current_state<=next_state;--在时钟上升沿，转换至下一状态
ENDIF;
ENDPROCESS;--由信号current_state将当前状态值带出此进程，进入进程PRO
PROCESS（LOCK）--此进程中，在LOCK的上升沿，将转换好的数据锁入
BEGIN
IFLOCK='1'ANDLOCK'EVENTTHENREGL<=ina;
ENDIF;
ENDPROCESS;
withREGL（3downto0）select
outa（6downto0）<="0110000"when"0001",--1
"1101101"when"0010",--2
"1111001"when"0011",--3
"0110011"when"0100",--4
"1011011"when"0101",--5
"1011111"when"0110",--6
"1110000"when"0111",--7
"1111111"when"1000",--8
"1111011"when"1001",--9
"1110111"when"1010",--A
"0011111"when"1011",--b
"1001110"when"1100",--c
"0111101"when"1101",--d
"1001111"when"1110",--e
"1000111"when"1111",--f
"1111110"whenothers;--0
withREGL（7downto4）select
outa（13downto7）<="0110000"when"0001",--1
"1101101"when"0010",--2
"1111001"when"0011",--3
"0110011"when"0100",--4
"1011011"when"0101",--5
"1011111"when"0110",--6
"1110000"when"0111",--7
"1111111"when"1000",--8
"1111011"when"1001",--9
"1110111"when"1010",--A
"0011111"when"1011",--b
"1001110"when"1100",--c
"0111101"when"1101",--d
"1001111"when"1110",--e
"1000111"when"1111",--f
"1111110"whenothers;--0
ENDbehav;
7.交通灯控制器
计数器的程序
LibraryIeee;
UseIeee.Std_Logic_1164.All;
EntityCounterIs
Port
（Clock:
InStd_Logic;
Reset:
InStd_Logic;
Hold:
InStd_Logic;
Countnum:
BufferIntegerRange0To49）;
End;
ArchitectureBehaviorOfCounterIs
Begin
Process（Reset,Clock）
Begin
IfReset='1'Then
Countnum<=0;
ElsifRising_Edge（Clock）Then
IfHold='1'Then——当出现紧急情况时，计数器暂停计数
Countnum<=Countnum;
Else
IfCountnum=49Then
Countnum<=0;
Else
Countnum<=Countnum+1;
EndIf;
EndIf;
EndIf;
EndProcess;
End;
1控制器的程序
LibraryIeee;
UseIeee.Std_Logic_1164.All;
EntityControllerIs
Port
（Clock:
InStd_Logic;
Hold:
InStd_Logic;
Countnum:
InIntegerRange0To49;——前级计数器的计数值
Numa,Numb:
OutIntegerRange0To25;——倒计时数值的计数值
Reda,Greena,Yellowa:
OutStd_Logic;——控制东西方向红黄绿灯的亮灭
Redb,Greenb,Yellowb:
OutStd_Logic;——控制南北方向红黄绿灯的亮灭
Flash:
OutStd_Logic）;——用以指示七段数码管显示数字的闪烁
End;
ArchitectureBehaviorOfControllerIs
Begin
Process（Clock）
Begin
IfFalling_Edge（Clock）Then——计数器是上升沿改变计数值，此处下降沿读取
IfHold='1'Then
Reda<='1';
Redb<='1';
Greena<='0';
Greenb<='0';
Yellowa<='0';
Yellowb<='0';
Flash<='1';
Else
Flash<='0';
IfCountnum<=19Then
Numa<=20-Countnum;——计数器东西方向倒计时
Reda<='0';
Greena<='1';
Yellowa<='0';
Elsif（Countnum<=24）Then
Numa<=25-Countnum;
Reda<='0';
Greena<='0';
Yellowa<='1';
Else
Numa<=50-Countnum;
Reda<='1';
Greena<='0';
Yellowa<='0';
EndIf;
IfCountnum<=24Then——计数器南北方向倒计时
Numb<=25-Countnum;
Redb<='1';
Greenb<='0';
Yellowb<='0';
ElsifCountnum<=44Then
Numb<=45-Countnum;
Redb<='0';
Greenb<='1';
Yellowb<='0';
Else
Numb<=50-Countnum;
Redb<='0';
Greenb<='0';
Yellowb<='1';
EndIf;
EndIf;
EndIf;
EndProcess;
分位电路程序
LibraryIeee;
UseIeee.Std_Logic_1164.All;
EntityFenweiIs
Port（Numin:
InIntegerRange0To25;
Numa:
OutIntegerRange0To2;
Numb:
OutIntegerRange0To9）;
End;
ArchitectureBehaviorOfFenweiIs
Begin
Process（Numin）
Begin
IfNumin>=20Then
Numa<=2;
Numb<=Numin-20;
ElsifNumin>=10Then
Numa<=1;
Numb<=Numin-10;
Else
Numa<=0;
Numb<=Numin;
EndIf;
EndProcess;
End;
.4.1七段译码电路的程序
LibraryIeee;
UseIeee.Std_Logic_1164.All;
EntityDisplayoneIs
Port（
Clock:
InStd_Logic;
Flash:
InStd_Logic;
Qin:
InStd_Logic_Vector（3Downto0）;
Display:
OutStd_Logic_Vector（0To6）
）;
End;
ArchitectureDecoderOfDisplayoneIs
SignalTimeout:
IntegerRange0To63;
Begin
Process（Clock）
Begin
IfRising_Edge（Clock）Then
IfFlash='0'Then
Timeout<=0;
Else
IfTimeout=63Then
Timeout<=0;
Else
Timeout<=Timeout+1;
EndIf;
EndIf;
IfTimeout<31Then
CaseQinIs
When"0000"=>Display<="0111111";
When"0001"=
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