TS6700测试仪资料.docx

1、TS6700测试仪资料Table of ContentsCHAPTER 1 System Structure 1.1 Hardware Configuration3 1.2 Features of the Test System.3 1.3 Mainframe and Test Head.4 1.4 DC Measurement Functions.7CHAPTER 2 Load Board Structure 2.1 Performance Board Type.9 2.2 Load Board Overview.9 2.3 Pin Location.10 2.4 Load Board La

2、yout13 LCD pin, I/O pin, DC pin, UVI pin, HCLK pin 2.5 Pin Assignment Table.17CHAPTER 3 System File Structure 3.1 Software System22 3.2 Development and Operating Environment23 3.3 Integrated Environment.243.4 Directory Structure of EWS.253.5 Directory Structure (Integrated Environment).26 3.6 File M

3、anagement for Test Program.27 3.7 Software Program Architecture31 Main Program, Test Flow, Segment, Sample ProgramCHAPTER 4 Test Result Inspection 4.1 Data Log.35 4.2 Lot Summary36 4.3 Test Result.39 4.4 Statistical data.42 4.5 Wafer Summary45 4.6 Wafer Map48 4.7 Dialog Box.51CHAPTER 5 Command Refer

4、ence 5.1 Data set Commands.52 5.2 System Management Commands 52 5.3 Pattern/Fail Display Commands.52 5.4 Program Control Commands 53 5.5 Debugging Commands 53CHAPTER 6 Pattern Tool 6.1 How to use the pattern tool (Ver 2.2x).54 6.2 How to use the pattern tool (Classic)56 6.3 How to get the fail patte

5、rn to datalog file57CHAPTER 7 Shmoo Tool 7.1 How to use shmoo tool58CHAPTER 8 Module Monitor 8.1 How to use the module monitor61Chapter1 System Structure1.1 Hardware ConfigurationThis section explains the hardware configuration of the TS6700 test system.Basic System ConfigurationThe basic configurat

6、ion of the TS6700 test system with one test head is shown below. The test system consists of the mainframe, test head, test head power frame, and either the WOT or OCT for mass-production operations. If the test system is to be used for development purposes, an EWS will be required. Each component u

7、nit of the test system contains different hardware as shown in the right block diagram.1.2 Features of the Test SystemThis section explains main features of the TS6700 test system.Digital Pin (I/O Pin)TS6700 employs a per-pin architecture, which provides a timing generator and DC measurement unit on

8、 every digital pin (I/O pin). This improves flexibility in test planning and reduces pro-gram development time drastically.LCD PinA comparator is provided on every LCD pin, resulting in drastic reduction of functional tests time, compared to conventional comparator switching type test systems. In ad

9、dition, use of an active load on LCD pins can also reduce test time for open-/short-circuit tests and resistance measurement performed for devices having many pins.In the case of TFT drivers, high-accuracy single-range measurements can be performed for devices with up to medium voltage level.The tes

10、t system can accommodate up to 736 LCD pins, allowing the test system to be used for future LCD drivers having a large pin count.Multi-DUT MeasurementTS6700 allows up to two devices to be measured simultaneously per test head.Frequency/Time MeasurementThis function allows measurement of the frequenc

11、y of any digital pin and measurement of time difference between any digital pins. With the reciprocal type counter, high-accuracy measurement is possible irrespective of the frequency. For frequency measurement, a hysteresis for the threshold voltage can be set. LPF (100 kHz) can also be selected.1.

12、3 Mainframe, Test HeadThis section explains the mainframe and test head of TS6700 system.A. Mainframe QTC nest (tester controller)Accommodates CPU cards, hard disk unit, module controller and interface cards. PG nestAccommodates a pattern generator, rate generator, fail memory controller and trigger

13、 cards. PM nestAccommodates pattern memory cards (one pattern memory card per 16 pins). It also accommodates interface cards and serial pattern memory cards PMU nestAccommodates a maximum of 16 VI modules (maximum voltage: 32 V, maximum current: 31 mA). VI modules include PMU, LCDPMU and RVI. UVI ne

14、stAccommodates a maximum of 4 universal VI modules (maximum voltage: 128 V, maximum current: 1 A). MS nestAccommodates clock generator, waveform generator, waveform digitizer, digital signal processor and other cards. UPSAn Uninterrupted Power Supply is provided at the rear side of the mainframe to

15、back up the tester controller in case of power failure. System powerAccommodates power supplies required for the test system.B. Test Head Pin electronics card sectionEach pin electronics card accommodates 8 pins, and up to 14 pin electronics cards (i.e., 112 pins) can be installed in a test head. Th

16、ey can be installed in card slots 1 to 7 and 17 to 23 (card slots 8 to 16 are not provided). Therefore, pins 1 to 56 and 129 to 184 can be provided (pins 57 to 128 are not provided). Relationship between pin electronic card # and pin # is shown below. HCLK card sectionEach HCLK card accommodates 2 p

17、ins, and up to 2 HCLK cards (i.e., 4 pins) can be installed in a test head. In test programs, HCLK pins are treated as PIN modules. Thus, pin # 57, 58, 185 and 186 are assigned to the HCLK pins. Relationship between HCLK card # and pin # is shown below. Mini nestThe following cards are installed in

18、the mini nest.1. ITFM card: Interfaces the tester controller with test heads. This card can accommodate an STM (for time measurement). 2. LCDIFM card: Controls LCD cards. 3. LCDCKM card: Supplies the system clock to PE cards and LCD cards. 4. LCDIFA card: Receives signals from LCD cards and outputs

19、them through a multiplexer to the MS nest. It also supplies the offset voltage to the ranging section of LCD cards. LCD card sectionEach LCD card accommodates 16 pins, and up to 46 LCD cards (i.e., 736 pins) can be installed in a test head. They can be installed in LCD card slots 1 to 23 and 25 to 4

20、7 (LCD card slot 24 is not provided). Therefore, pins 1 to 368 and 385 to 752 can be provided (pins 369 to 384 are not provided). Relationship between LCD card # and pin # is shown right. IDDQ card sectionEach IDDQ card accommodates 2 pins, and up to 2 IDDQ cards (i.e., 4 pins) can be installed in a

21、 test head. Relationship between IDDQ card # and pin # is shown below.If no IDDQ cards are installed, a PF card will be installed instead to monitor nest power. DC card sectionEach DC card accommodates 12 pins, and up to 2 DC cards (i.e., 24 pins) can be installed in a test head. Relationship betwee

22、n DC card # and pin # is shown below. Switch boxThe switch box has switches and an indicating LED in the following functions: a switch used to fix a performance board to the test head, a switch used to release the performance board, a switch used to turn SA power ON/OFF, and an LED used to indicate

23、that power is currently supplied to the test head. The position of the switch box can be changed according to how its used (e.g., wafer test, final test).1.4 DC Measurement FunctionsA. UVI (Universal VI) Module UVI modules are provided as device power supplies, and can also be connected via the DC m

24、atrix line to perform DC parametric measurements that exceed current ranges of PMU, LCDPMU, and RVI. In addition, UVI modules provide a function of IDDQ test. Outputs of the UVI modules are connected to IDDQ cards as shown in the table. The output voltage range is from +128V to -128 V. The output cu

25、rrent ranges are 30uA, 300uA, 3 mA, 30 mA, 60 mA, 250 mA, 1 A. When connected via the DC matrix line, the maximum output voltage/current will be limited to 64 V/250 mA. B. I/O Pin Shared PMU PMU modules are provided for DC parametric measurements that exceed voltage/currentranges of SVI. A specific

26、channel is assigned to each I/O pin as shown in the table below. The output voltage range is from +15V to 15V. The output current ranges are 3uA, 30uA, 300uA, 3mA, and 30mA. C. LCDPMU LCDPMU modules are provided for DC parametric measurements of LCD pins. A specific channel is assigned to each LCD p

27、in as shown in the table below. The output voltage range is from +32V to 32V. The output current range are 3uA, 30uA, 300uA, 3mA, and 30mA.D. I/O Per-Pin DC (SVI) This function is provided per-pin on the pin electronics card, and is mainly used for measurement of device input leak current and short-

28、circuit contact test. VFIM and IFVM measurements can be performed. The output voltage range is from +8 V to -2.5 V. The output current ranges are 10uA and 250uA. E. RVI RVI modules are provided to supply the reference power to the LCD drivers, and up to 24 channels can be installed. The output volta

29、ge range is from +32V to 32V. The output current ranges are 3uA, 30uA, 300uA, 3mA, and 30mA.F. DC Measurement Block DiagramChapter2 Load board Structure2.1 Performance Board TypeA. Performance board compatible with TS6700 series probe cards (PFB-A or PFB-D)Probe cards developed for TS700 can be used

30、 with TS6700 without any modifications.LCD pins: 512 (max.), I/O pins: 62 (max.)B. Full-pin performance board (PFB-B)This board supports full pin configuration of TS6700.LCD pins: 480 (max.), I/O pins: 64 (max.)C. Full-pin performance board (PFB-C)This board supports full pin configuration of TS6700