CPU报告04008409沈昊骍.docx

CPU报告04008409沈昊骍.docx

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CPU报告04008409沈昊骍

ComputerOrganizationandArchitectureCourseDesign

CPU

1.Purpose

ThepurposeofthisprojectistodesignasimpleCPU（CentralProcessingUnit）.ThisCPUhasbasicinstructionset,andwewillutilizeitsinstructionsettogenerateaverysimpleprogramtoverifyitsperformance.Forsimplicity,wewillonlyconsidertherelationshipamongtheCPU,registers,memoryandinstructionset.Thatistosayweonlyneedconsiderthefollowingitems:

Read/WriteRegisters,Read/WriteMemoryandExecutetheinstructions.

AtleastfourpartsconstituteasimpleCPU:

thecontrolunit,theinternalregisters,theALUandinstructionset,whicharethemainaspectsofourprojectdesignandwillbestudied.

2.Topblockdiagramofthesimplecomputer

3.Thefunctionsofthecomputer

MAR（MemoryAddressRegister）

MARcontainsthememorylocationofthewordtobereadfromthememoryor

writtenintothememory.Here,READoperationisdenotedastheCPUreadsfrom

memory,andWRITEoperationisdenotedastheCPUwritestomemory.Inour

design,MARhas8bitstoaccessoneof256addressesofthememory.

MBR（MemoryBufferRegister）

MBRcontainsthevaluetobestoredinmemoryorthelastvaluereadfrommemory.MBRisconnectedtotheaddresslinesofthesystembus.Inthedesign,MBRhas16bits.

PC（ProgramCounter）

PCkeepstrackoftheinstructionstobeusedintheprogram.Inourdesign,PChas8bits.

IR（InstructionRegister）

IRcontainstheopcodepartofaninstruction.Inourdesign,IRhas8bits.

BR（BufferRegister）

BRisusedasaninputofALU,itholdsotheroperandforALU.Inourdesign,BRhas16bits.

ALU（Accumulator）

ACCholdsoneoperandforALU,andgenerallyACCholdsthecalculationresultof

ALU.Inourdesign,ACChas16bits.

TheALUsupports：

Arithmeticoperation:

ADD,SUB,MPYbetweenACCandBR;

Logicoperation：

AND,ORbetweenACCandBRbitbybit.

NOTcomplementtheACCbitbybit.

SHIFTR\SHIFTLshifttheACCtoright\leftonebit,theshiftr_inandshiftl_inareinputsforSHIFTRandSHIFTLoperationrespectively.TheresultsarestoredintoACCatthepositive-edgeofCLK.

MR（MultiplierRegister）

MRisusedforimplementingtheMPYinstruction,holdingthemultiplieratthe

beginningoftheinstruction.Whentheinstructionisexecuted,itholdshighpartofthe

product.

LPM_RAM_DQ（Memory）

LPM_RAM_DQisaRAMwithseparateinputandoutputports,itworksasmemory,anditssizeis256×16.Althoughit’snotaninternalregisterofCPU,weneedittosimulateandtesttheperformanceofCPU.

LPM_ROM（Controlmemory）

LPM_ROMisaROMwithinputandoutputports,itworksasapartofMicroprogrammedControlUnit.Itssizeis256×32.Microinstructionsandmicroprogramisstoredinit.

CONTROL_UNIT

CONTROL_UNITisacontrolunit,accordingtoopcodeitreceived,itwilldeterminethewhataddresscarbuswilltake.

4.Thecontrolflowchartofeachinstruction

（1）LOAD:

（2）STORE:

（3）ADD:

（4）SUB:

（5）SHIFTR

:

（6）SHIFT

L:

（7）AND:

（8）OR:

（9）NOT:

（10）JMP:

（11）MPY：

MBR←memory

IRopcode←MBR

N

Y

PC←PC+1

PC←MBR[7:

0]

MAR←PC

Bitinread-onlycontrolmemory

（BitofROM）

Micro-operation

Controlsignalname

C0

CAR←CAR+1

IncreaseCAR

C1

CAR←**

Controladdressing

C2

CAR←0

ResetCAR

C3

MBR←memory

ReadRAM

C4

IRopcode←MBR（15..8）

MBRintoIRopcode

C5

MAR←MBR[7..0]

MBRintoMAR

C6

PC←PC+1

IncreasePC

C7

BR←MBR

MBRintoBR

C8

ACC←0

reset_ACC

C9

ACC←ACC+BR

ADD

C10

MAR←PC

PCintoMAR

C11

memory←MBR

RAM_write

C12

MBR←ACC

ACCintoMBR

C14

PC←MBR

MBRintoPC

C15

PC←0

Reset_PC

C16

ACC←ACC-BR

SUB

C17

ShiftACCtoright

SHIFTR

C18

MR←ACC*BR（H）

MPY（H）intoMR

C24

ACC←ACC*BR

Mpy（L）

C25

ShiftACCtoleft

SHIFTL

C26

ACC←NOTACC

NOT

C27

ACC←ACCorBR

OR

C28

ACC←ACCandBR

AND

5.Themeaningofallthecontrolsignals

6.ThecontentoftheROM

WIDTH=32;

DEPTH=256;

ADDRESS_RADIX=HEX;

DATA_RADIX=HEX;

CONTENTBEGIN

0:

00000009C3,C0MBR←memory，CAR←CAR+1

1:

00000011C4,C0IRopcode←MBR15-8，CAR←CAR+1

2:

00000002C1CAR←**

[3..f]:

0；

10:

00000061C5,C6,C0load:

MAR←MBR7-0,PC←PC+1,CAR←CAR+1

11:

00000009C3,C0MBR←memory,,CAR←CAR+1

12:

00000181C8,C7,C0ACC←0,BR←MBR,CAR←CAR+1

13:

00000201C9,C0ACC←ACC+BR,CAR←CAR+1

14:

00000404C10,C2MAR←PC,CAR←0

[15..1f]:

0；

20:

00000061C5,C6,C0store:

MAR←MBR7-0,PC←PC+1,CAR←CAR+1

21:

00001001C12,C0MBR←ACC,CAR←CAR+1

22:

00000801C11,C0memory←MBR,CAR←CAR+1

23:

00000404C10,C2MAR←PC，CAR←0

[24..2f]:

0;

30:

00000061C5,C6,C0add:

MAR←MBR7-0,PC←PC+1,CAR←CAR+1

31:

00000009C3,C0MBR←memory,CAR←CAR+1

32:

00000081C7,C0BR←MBR,CAR←CAR+1

33:

00000201C9,C0ACC←ACC+BR,CAR←CAR+1

34:

00000404C10,C2MAR←PC,CAR←0,

[35..3f]:

0;

40:

00000061C5,C6,C0sub:

MAR←MBR7-0,PC←PC+1,CAR←CAR+1

41:

00000009C3,C0MBR←memory,CAR←CAR+1

42:

00000081C7,C0BR←MBR,CAR←CAR+1

43:

00010001C16,C0ACC←ACC-BR,CAR←CAR+1

44:

00000404C10,C2MAR←PC,CAR←0

[45..4f]:

0

50:

00008104C8,C15,C2,halt:

ACC←0,CAR←0,PC←0

[51..5f]:

0;

60:

00000061C5,C6,C0and:

MAR←MBR7-0,PC←PC+1,CAR←CAR+1

61:

00000009C3,C0MBR←memory,CAR←CAR+1

62:

00000081C7,C0BR←MBR,CAR←CAR+1

63:

10000001C28,C0ACC←ACCandBR,CAR←CAR+1

64:

00000404C10,C2MAR←PC，CAR←0

[65..6f]:

0;

70:

00000061C5,C6,C0or:

MAR←MBR7-0,PC←PC+1,CAR←CAR+1

71:

00000009C3,C0MBR←memory,CAR←CAR+1

72:

00000081C7,C0BR←MBR,CAR←CAR+1

73:

08000001C27,C0ACC←ACCorBR,CAR←CAR+1

74:

00000404C10,C2MAR←PC,CAR←0

[75..7f]:

0;

80:

04000041C26,C6,C0not:

ACC←notACC,CAR←CAR+1

81:

00000404C10,C2MAR←PC,CAR←0

[82..8f]:

0;

90:

00020044C17,C6,C2shiftr:

ACC←ACC>>1,CAR←CAR+1

91:

00000404C10,C2MAR←PC,CAR←0

[92..9f]:

0;

a0:

02000044C25,C6,C2shiftl:

ACC←ACC<<1,CAR←CAR+1

a1:

00000404C10,C2MAR←PC,CAR←0

[a2..af]:

0;

b0:

00000061C5,C6,C0mpy:

MAR←MBR7-0,PC←PC+1,CAR←CAR+1

b1:

00000009C3,C0MBR←memory,CAR←CAR+1

b2:

00000081C7,C0BR←MBR,CAR←CAR+1

b3:

01000001C24,C0ACC←ACC*BR（L）,CAR←CAR+1

b4:

00040001C18,C0MR←ACC*BR（H）,CAR←CAR+1

b5:

00000404C10,C2MAR←PC,CAR←0

[b8..ef]:

0

F0:

00000041C6,C0jumpez:

（IFflag=1）PC←PC+1,CAR←CAR+1

F1:

00000404C10,C2CAR←0,MAR←PC

F2:

00004001C14,C0（IFflag=0）PC←MBR7-0,CAR←CAR+1

F3:

00000404C10,C2CAR←0,MAR←PC

[F4..Ff]:

0;

7.TestandResults:

1.Calculatethesumofallintegersfrom1to100.

AssumeintheLPM_RAM_DQ:

sumisstoredatlocationa4,

tempisstoredatlocationa3,

thecontentoflocationa0is0,

thecontentoflocationa1is1,

thecontentoflocationa2is100

thecontentoflocationa3is0,

thecontentoflocationa4is0,

SothecontentoftheLPM_RAM_DQcanbe:

WIDTH=16;

DEPTH=256;

ADDRESS_RADIX=HEX;

DATA_RADIX=HEX;

CONTENTBEGIN

0:

02a0;--loadA0

1:

01a4;--storeA4sum=0

2:

02a2;--loadA2

3:

01a3;--storeA3temp=100

4:

02a4;--loop:

loadA4loop=04

5:

03a3;--addA3

6:

01a4;--storeA4sum=sum+temp

7:

02a3;--loadA3

8:

04a1;--subA1

9:

01a3;--storeA3temp=temp-1

a:

0504;--jumploopiftemp>=0gotoloop

b:

HALT;--halt

[c..9f]0;

a0:

0;

a1:

1;

a2:

0064;

a3:

0;--temp

a4:

0;--sum

[a5..ff]:

0000;

END;

Theresultisasfollows:

WecanseethatthesumisA4=5050.

2.TesttheMPYinstruction

（1）AssumeintheLPM_RAM_DQ:

thecontentoflocationa0is6,

thecontentoflocationa1is5,

Calculatea0*a1.

SothecontentoftheLPM_RAM_DQcanbe:

WIDTH=16;

DEPTH=256;

ADDRESS_RADIX=HEX;

DATA_RADIX=HEX;

CONTENTBEGIN

0:

02a0;

1:

08a1;

[2..9f]:

0000;

A0:

0006;

A1:

0005;

[A2..FF]:

0000;

END;

Theresultisasfollows:

Wecanseetheresultof（a0*a1）is[mracc]=（0000001E）H=（30）D

（2）AssumeintheLPM_RAM_DQ:

thecontentoflocationa0is-6,

thecontentoflocationa1is5,

Calculatea0*a1.

SothecontentoftheLPM_RAM_DQcanbe:

WIDTH=16;

DEPTH=256;

ADDRESS_RADIX=HEX;

DATA_RADIX=HEX;

CONTENTBEGIN

0:

02a0;

1:

08a1;

[2..9f]:

0000;

A0:

FFFA;

A1:

0005;

[A2..FF]:

0000;

END;

Theresultisasfollows:

Wecanseetheresultof（a0*a1）is[mracc]=（FFFFFFE2）H=（-30）D

（3）AssumeintheLPM_RAM_DQ:

thecontentoflocationa0is-6,

thecontentoflocationa1is-5,

Calculatea0*a1.

SothecontentoftheLPM_RAM_DQcanbe:

WIDTH=16;

DEPTH=256;

ADDRESS_RADIX=HEX;

DATA_RADIX=HEX;

CONTENTBEGIN

0:

02a0;

1:

08a1;

[2..9f]:

0000;

A0:

FFFA;

A1:

FFFB;

[A2..FF]:

0000;

END;

Theresultisasfollows:

Wecanseetheresultof（a0*a1）is[mracc]=（0000001E）H=（30）D