数字电路与逻辑设计12.ppt

数字电路与逻辑设计12.ppt

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,DigitalFundamentalsTenthEditionFloyd,Chapter12,Summary,Mostinputsignalstoanelectronicsystemstartoutasanalogsignals.Forprocessing,thesignalisnormallyconvertedtoadigitalsignalbysamplingtheinput.,Sampling,Beforesampling,theanaloginputmustbefilteredwithalow-passanti-aliasingfilter.Thefiltereliminatesfrequenciesthatexceedacertainlimitthatisdeterminedbythesamplingrate.,Summary,Tounderstandtheneedforananti-aliasingfilter,youneedtounderstandthesamplingtheoremwhichessentiallystates:

Anti-aliasingFilter,wherefsample=samplingfrequency,fa（max）=highestharmonicintheanalogsignal,Statedasanequation,fsample2fa（max）,Inordertorecoverasignal,thesamplingratemustbegreaterthantwicethehighestfrequencyinthesignal.,Ifthesignalissampledlessthanthis,therecoveryprocesswillproducefrequenciesthatareentirelydifferentthanintheoriginalsignal.These“masquerading”signalsarecalledaliases.,Summary,Theanti-aliasingfilterisalow-passfilterthatlimitshighfrequenciesintheinputsignaltoonlythosethatmeettherequirementsofthesamplingtheorem.,Anti-aliasingFilter,Unfilteredanalogfrequencyspectrum,Overlapcausesaliasingerror,f,fsample,Samplingfrequencyspectrum,Thefilterscutofffrequency,fc,shouldbelessthanfsample.,Toprocessnaturallyoccurringanalogquantitieswithadigitalsystem,theanalogsignalisconvertedtodigitalformaftertheanti-aliasingfilter.,Summary,Analog-to-DigitalConversion,Thefirststepinconvertingasignaltodigitalformistouseasample-and-holdcircuit.Thiscircuitsamplestheinputsignalataratedeterminedbyaclocksignalandholdsthelevelonacapacitoruntilthenextclockpulse.,Apositivehalf-wavefrom0-10Visshowninblue.Thesample-and-holdcircuitproducesthestaircaserepresentationshowninred.,0V,10V,Summary,Thesecondstepistoquantizethesestaircaselevelstobinarycodedformusingananalog-to-digitalconverter（ADC）.Thedigitalvaluescanthenbeprocessedbyadigitalsignalprocessororcomputer.,0V,10V,Example,Whatisthemaximumunsignedbinaryvalueforthewaveform?

Solution,10V=10102V.Thetableliststhequantizedbinaryvaluesforallofthesteps.,Peak=10V,Analog-to-DigitalConversion,Summary,Mostsignalshavehigherfrequencyharmonicandnoise.FormostADCs,thesamplingandfiltercutofffrequenciesareselectedtobeabletoreconstructthedesiredsignalwithoutincludingunnecessaryharmonicsandnoise.,Anti-aliasingFilter,AnexampleofareasonablesamplingrateisinadigitalaudioCD.ForaudioCDs,samplingisdoneat44.1kHzbecauseaudiofrequenciesabove20kHzarenotdetectablebytheear.,Question,Whatcutofffrequencyshouldananti-aliasingfilterhaveforadigitalaudioCD?

Answer,Lessthan22.05kHz.,Summary,Sample-and-HoldandADC,Followingtheanti-aliasingfilter,isthesample-and-holdcircuitandtheanalog-to-digitalconverter.Atthispoint,theoriginalanalogsignalhasbeenconvertedtoadigitalsignal.,ManyICscanperformbothfunctionsonasinglechipandincludetwoormorechannels.Foraudioapplications,theAD1871isanexampleofastereoaudioADC.,Samplesheldforoneclockpulse,01000101,11001010,Summary,Analog-to-DigitalConversionMethods,TheflashADC:

TheflashADCusesaserieshigh-speedcomparatorsthatcomparetheinputwithreferencevoltages.FlashADCsarefastbutrequire2n1comparatorstoconvertananaloginputtoann-bitbinarynumber.,Question,Howmanycomparatorsareneededbya10-bitflashADC?

Answer,1023,Summary,Analog-to-DigitalConversionMethods,Thedual-slopeADC:

1.Thedual-slopeADCintegratestheinputvoltageforafixedtimewhilethecountercountston.,2.ControllogicswitchestotheVREFinput.,-V,HIGH,HIGH,2.Afixed-sloperampstartsfromVasthecountercounts.Whenitreaches0V,thecounteroutputislatched.,Summary,Analog-to-DigitalConversionMethods,ThesuccessiveapproximationADC:

1.StartingwiththeMSB,eachbitinthesuccessiveapproximationregister（SAR）isactivatedandtestedbythedigital-to-analogconverter（DAC）.,2.Aftereachtest,theDACproducesanoutputvoltagethatrepresentsthebit.,3.Thecomparatorcomparesthisvoltagewiththeinputsignal.Iftheinputislarger,thebitisretained;otherwiseitisreset（0）.,SAR,DAC,Vout,Parallelbinaryoutput,CLK,D0,D1,D2,D3,Serialbinaryoutput,Inputsignal,Comparator,（MSB）,（LSB）,Themethodisfastandhasafixedconversiontimeforallinputs.,Summary,Analog-to-DigitalConversionMethods,AnintegratedcircuitsuccessiveapproximationADCistheADC804.ThispopularADCisan8-bitconverterthatcompletesaconversionin64clockperiods（100ms）.,Summary,Analog-to-DigitalConversionMethods,Thesigma-deltaADC:

Withsigma-deltaconversion,thedifferencebetweentwosamplesoftheanaloginputsignalintegratedandquantized.Thedensityof1sattheoutputisproportionaltotheinputsignal.,Summary,Analog-to-DigitalConversionMethods,Oneoptionforthesigma-deltamethodistocounttheone-bitquantizedoutputforasetinterval.Theoutputofthecounterislatchedwiththeparallelbinarycode.,Sigma-deltaADCscanhavehighresolutionandhaveadvantagesforrejectingnoisesignals（suchas60Hzpowerlineinterference）.TheyareavailableinICswithinternalprogrammableamplifiers.Forthesereasons,theyarewidelyusedininstrumentationapplications.,Summary,Digital-to-AnalogConversionMethods,Binary-weighted-inputDAC:

Thebinary-weighted-inputDACisabasicDACinwhichtheinputcurrentineachresistorisproportionaltothecolumnweightinthebinarynumberingsystem.ItrequiresveryaccurateresistorsandidenticalHIGHlevelvoltagesforaccuracy.,TheMSBisrepresentedbythelargestcurrent,soithasthesmallestresistor.Tosimplifyanalysis,assumeallcurrentgoesthroughRfandnoneintotheop-amp.,MSB,LSB,8R,4R,2R,R,Rf,Vout,Analogoutput,D0,D1,D2,D3,Summary,Digital-to-AnalogConversionMethods,Example,Acertainbinary-weighted-inputDAChasabinaryinputof1101.IfaHIGH=+3.0VandaLOW=0V,whatisVout?

Solution,+3.0V,+3.0V,+3.0V,0V,120kW,60kW,30kW,15kW,10kW,Rf,Vout=IoutRf=（0.325mA）（10kW）=,3.25V,Vout,Summary,Digital-to-AnalogConversionMethods,R-2Rladder:

TheR-2Rladderrequiresonlytwovaluesofresistors.BycalculatingaTheveninequivalentcircuitforeachinput,youcanshowthattheoutputisproportionaltothebinaryweightofinputsthatareHIGH.,2R,R,R,R,2R,2R,2R,2R,Rf=2R,Inputs,D0,D1,D2,D3,EachinputthatisHIGHcontributestotheoutput:

Vout,whereVS=inputHIGHlevelvoltagen=numberofbitsi=bitnumber,R1,R3,R5,R7,R2,R4,R6,R8,Foraccuracy,theresistorsmustbepreciseratios,whichiseasilydoneinintegratedcircuits.,Summary,Digital-to-AnalogConversionMethods,Rf=50kW,0V,+5.0V,Vout,R1,R3,R5,R7,R2,R4,R6,R8,Example,AnR-2Rladderhasabinaryinputof1011.IfaHIGH=+5.0VandaLOW=0V,whatisVout?

50kW,25kW,Solution,50kW,50kW,50kW,50kW,25kW,25kW,+5.0V,+5.0V,D0,D1,D2,D3,Applyingsuperposition,Vout=,3.43V,ApplytoallinputsthatareHIGH,thensumtheresults.,Summary,ResolutionandAccuracyofDACs,TheR-2RladderisrelativelyeasytomanufacturerandisavailableinICpackages.DACsbasedontheR-2Rnetworkareavailablein8,10,and12-bitversions.Theresolutionisanimportantspecification,definedasthereciprocalofthenumberofstepsintheoutput.,Question,WhatistheresolutionoftheBCN31R-2Rladdernetwork,whichhas8-bits?

Answer,281=255,1/255=0.39%,Theaccuracyisanotherimportantspecificationandisderivedfromacomparisonoftheactualoutputtotheexpectedoutput.FortheBCN31,theaccuracyisspecifiedasLSB=0.2%.,Summary,ReconstructionFilter,ReconstructionFilter,OutputoftheDAC,Finalanalogoutput,Afterconvertingadigitalsignaltoanalog,itispassedthroughalow-pass“reconstructionfilter”tosmooththestairstepsintheoutput.Thecutofffrequencyofthereconstructionfilterisoftensettothesamelimitastheanti-aliasingfilter,toblockhigherharmonicsduetothedigitizingprocess.,Summary,Adigitalsignalprocessor（DSP）isoptimizedforspeedandworkinginrealtime（aseventshappen）.Itisbasicallyaspecializedmicroprocessorwithareducedinstructionset.,DigitalSignalProcessing,Afterfilteringandconvertingtheanalogsignaltodigital,theDSPtakesover.Itmayenhancethesignalinsomepredeterminedway（reducingnoiseorechoes,improvingimages,encryptingthesignal,etc.）.Thesignalcanthenbeconvertedbacktoanalogformifdesired.,Summary,BecausespeedisimportantinDSPapplications,assemblylanguageisfrequentlyusedbecauseingeneralitexecutesfaster.,DigitalSignalProcessing,AgeneralblockdiagramoftheTMS320C6000seriesDSP,SelectedKeyTerms,NyquistfrequencyQuantizationAnalog-to-digitalconverter（ADC）DSPDigital-to-analogconverter（DAC）,Thehighestsignalfrequencythatcanbesampledataspecifiedsamplingfrequency;afrequencyequalorlessthanhalfthesamplingfrequency.,Theprocesswherebyabinarycodeisassignedtoeachsampledvalueduringanalog-to-digitalconversion.,Acircuitusedtoconvertananalogsignaltodigitalform.,DigitalsignalProcessor;aspecialtypeofmicroprocessorthatprocessesdatainrealtime.,Acircuitusedtoconvertadigitalsignaltoanalogform.,1.Ifananti-aliasingfilterisnotusedindigitizingasignaltherecoveryprocessa.isslowedb.mayincludealiassignalsc.willhavelessnoised.alloftheabove,2008PearsonEducation,Quiz,2.Ananti-aliasingfiltershouldhavea.fcmorethan2timestheNyquistfrequencyb.fcequaltotheNyquistfrequencyc.fcmorethanfsampled.fclessthanfsample,2008PearsonEducation,Quiz,3.Thenumberofcomparatorsrequiredina10-bitflashADCisa.255b.511c.1023d.4095,2008PearsonEducation,Quiz,4.Theblockdiagramisforasuccessive-approx