外文翻译微处理器报告.docx

外文翻译微处理器报告.docx

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外文翻译微处理器报告

附录A　科技文章摘译

MICROPROCESSORREPORT

AtmelAVRBringsRISCto8-BitWorld

BetterPerformanceThanOther8-BitChipsWithSameLowCost

ByJimTurley

Provingtheadagethatalltechnologieseventuallyfilterdownintocommodityproducts,AtmelhasbroughtRISCdesignphilosophyto8-bitmicro-controllers.DubbedAVR,thisnewarchitectureprovidesalltheusualbenefitsofRISC:

fasterclockrates,betterperformance,andmoreefficientcompileroptimization.Atmelalsopromisesbettercodedensityandlowercostthancomparable8-bitmicro-controllers.

AVRcompeteswithseveralwell-establishedmicro-controllerdynastiessuchasthe6805,68HC11,and8051.CompetitionalsocomesfromMicrochip’sPICfamily,amoremoderndesignthat’sexpandedrapidlyinthepastfewyears.AtmelhopesAVRwillappealtoembeddeddesignerswhoarewillingtotackleanewarchitecturetogetmoreperformancethantheentrenchedmicro-controllerfamiliescanprovide.

AVRisthefirstin-houseCPUdesignfromAtmel,abillion-dollarcompanybetterknownforitsflashmemoryandE2PROMproducts.Thecompanyalsosellsadozenflash-basedderivativesofthepopular8051family,whichitproducesunderlicensefromIntel.

DesignMeldsRISCandMicro-controllerIdeas

TheCPUresemblesmostRISCprocessorsbuthassmallerregisters.ItwasoriginallydevelopedbyapairofresearchersinTrondheim,Norway,beforetheirconsultancywasacquiredbyAtmelin1995.CoreCPUdevelopmentstilltakesplaceinNorway,whilememoryandperipheraldevelopmentiscenteredinAtmel’sSanJose（Calif.）facility.

Thecorefeatures32identical8-bitregisters,asFigure1shows.Anyregistercanholdaddressesordata.Since8-bitaddresspointersarefairlyworthlesseveninan8-bitdevice,thelastsixregisterscanbeusedinpairs,asaddresspointers.DubbedX,Y,andZ,thesethreemeta-registerscanbeusedforanyloadorstoreoperation.Thepointerscanbepostincrementedorpredecrementedattheprogrammer’soption.Finally,a6-bitdisplacementcanbeaddedtothecontentsofthepointer,ausefuloptionforaddressingarrayelements.ThismodeisnotavailablefortheXpointer;thatopcodeisreservedfortheLDI（loadimmediateconstant）instruction.

　　Figure1.Unlikeother8-bitcontrollers,AVRhasasetof328-bitregisters.Thelastsixregisterscanbepairedtoformthreeaddresspointers.

　　Aswithmanylow-endmicro-controllers,theregisterfileismappedintotheaddressspace,andviceversa.Thefirst32bytesofmemory,0x00–0x1F,correspondtoregistersR0–R31.Thechip’sstatusregister—whichcontainstheoverflow,carry,sign,andotherflags—aswellasother“internal”registersarealsomemorymapped.Thisallowsanyregistertobemanipulatedusingstandardmemoryreferencesinsteadofspecialcontrol-registerinstructions.

Forallintentsandpurposes,theCPUhasnopipeline.Itretrievesbothsourceoperands,executestheinstruction,andstorestheresultinasingleclockcycle.Branchlatencyisoneclockfortakenbranches.Alloperationsareregister-to-register;thechipfollowsastrictload/storemodel.

ThegreatmajorityofAVRinstructionsare16bitslong.Onlyfour32-bitinstructionsexist,allowinglimiteduseofabsolute16-bitaddressing.AVRseparatestheprogramanddataspaces;althoughdatapointerscanbe16bits,thePC（programcounter）isonly12bitswide,for8Kofcodespace.

　　InstructionSetAsRegularAsPossible

　　Thecompactinstructionsetnecessarilyforcessomecompromises,thefirstofwhichaffectsimmediatevalues（literals）.Veryfewinstructionsacceptimmediatevalues,andthosethatdo（ADIW,SUBI,ORI,etc.）workonlyontheupperhalf（R16–R31）oftheregisterset,asTable1shows.Evenaftershavingabitfromtheoperand-specifiedfield,theseinstructionssometimeshaveroomforonly6-bitimmediatevalues.

Table1.Atmel’sAVR8-bitRISCinstructionsetfollowsastrictload/storemodel,withafewsimpleindirectaddressingmodes,includingpostincrementandpreferment.Thearchitecturealsoincludesanumberofindividualbit-manipulationinstructions.

TheADIWandSBIWinstructions（add/subtractimmediatefromword）areevenmorerestrictive,operatingononlythelasteightregisters,R24–R31.Theseinstructionsaremeantprimarilytoaddsmalloffsets（0–63bytes）totheX,Y,andZpointers.

Thereisawealthofconditionalbranchinstructions:

namely,twoforeachoftheeightflagsinthestatusregister.Withlittle7-bitoffsets,theseinstructionscandeflectexecutiononly64instructionsineitherdirection.Forbiggerdisplacements,RJMPcanshiftcodeby2K,whichisusuallyplenty,giventhechip’ssmallcodespace.

AVRalsohasacollectionofinteresting“skip”operations（SBRC,SBRS,SBIC,andSBIS）thatskipoverthenextinstructionifanybitinanyregisterissetorclear.Iftheskippedinstructionisalong-displacementjump,theseskipscanbeusedtoeffectivelycreateconditionallong-displacementbranches.Alternatively,theycanbeusedtoskipasinglearithmeticorlogicaloperationinastringofoperations,creatingconditionaloperationssomewhatsimilartoARM’s.

NoneoftheAVRchipshasanativemultiplyoperation—muchlessadivide—althoughonehasbeendefined.Asdefined,MULmultipliesanytwo8-bitregistersanddepositsthe16-bitresultinR0andR1.Whenimplemented,MULexecutesinjusttwoclockcycles,whichisfivetimesfasterthanthe68HC11’s10clocks;evenMotorola’snewer68HC12（seeMPR5/27/96,p.1）needs3clocks.AtmelexpectstodeployitsmultiplierinfutureAVRchipsasclockspeedsincreaseandthechipstakeonsimplesignal-processingtasks.

InstructionsAreRichinBitManipulation

Aswithmostmicro-controllers,theAVRfamilyhasahostofbit-twiddlingoptions,including16explicitinstructionstosetandcleareveryflaginitsstatusregister.Thisseemslikealopsideduseofopcodespace;thesameresultcouldhavebeenachievedwithnormallogicaloperations.Fordeeplyembeddedapplications,however,thiswasprobablytherightchoice.Maskingoperationsusepreciousaddresspointersandoneormoreregisters;theSEx/CLxinstructionsuseneither.

ThechipcanalsosetorclearanybitinanygeneralpurposeorI/Oregister;SERandCLRwipethecontentsofanentireregisteratonce.SBRandCBR,whichsetorclearmultiplebitsatatime,arealiasesforORIandANDI,respectively.

InitialLaunchIncludesFiveParts

AtmellauncheditsAVRproductlinewithfourbasicchips:

the90S1200,the’2313,the’4414,andthe’8515.Thelatterthreedevicesareverysimilar,differingmainlyintheamountofmemoryonthechip:

2K,4K,or8Kofflash,withtheamountofon-chipSRAMandE2PROMalsoincreasing.

Theruntofthelitter,the1200,hasonly1Kofflashmemory,noSRAM,noperipherals,andarestrictedinstructionset.WithneitherSRAMnoranexternalbus,the1200mustuseon-chipflashfordatastorage,whichwillslowexecutionconsiderablyunlessprogrammerscangetbywithjugglingtheregistersetalone.The1200arealsotheonlychipinthefamilycurrentlyinproduction.In1,000-unitquantities,the20-pin90S1200sellsforapaltry$1.65.

It’snotoftenthatthenumberofdatabitsoutnumbersthepinsonthepackage,butAtmelmanagedtogetclosewithits1220device,an8-pinversionofthe1200.Afterpower,ground,andcrystalconnections,onlyfourpinsarefreeforI/O.MostAVRchipscomein20-pinDIPorSOICpackages,whichprovideaccesstomoreI/Olines;onlyina40-pinpackagedothechipsbondouttheiraddressanddatabusesforaccesstoexternalmemory.

AllthepartsarefabricatedonAtmel’sfour0.8-microntwo-layer-metalfablinesinColoradoSpringsandRousset（France）.ThisisthesamememoryprocessAtmelusesforitsE2PROMandflashdevices,andforits8051chipswithintegratedflash.The1200measureabout24mm2overall,andasthediephotoinFigure2shows,thechipisnearlyalllogic.Memoryprocessestypicallydon’tproduceverycompact（orfast）logic,butmostAVRchipswillbedominatedbymemoryandperipherals,andclockspeedsaren’tveryhigh.

Figure2.The90S1200measuresabout4.3´5.5mminAtmel’s0.8-microntwo-layer-metalflash-memoryprocess.

ForOnce,RISCTechniquesImproveCodeDensity

It’ssometimeshardtogetexcitedabout8-bitprocessors,yetAtmel’sAVRdesignisasdifferentfromothersinitsclassasthefirstRISCmachinewasfrombigsystemsmorethanadecadeago.Withitslargeregisterfileandorthogonalinstructionset,AVRisfarmoremodernthanitscompetitors.

Atmel’snewCPUwillbeparticularlyappealingtoprogrammersmovingdownthemicroprocessorfoodchainfrom32-bitor16-bitchipsandwhoareaccustomedtoflexibleregistersets.Forprogrammersmovingupfrom,say,the8051,AVRwillbearealeye-opener.

Forexample,the8051,6805,andPICallmakedowithasingleaccumulator;the　68HC11and’HC12havejusttwo.ThismakesAVReasiertoprogramattheassemblylevelandeasiertooptimizewithacompiler.Thebigregistersetreducesdependenceonmemory,whichimprovesspeedandshrinksdata-storagerequirements.

Counterintuitively,AVR’sRISC-likeinstructionsetalsohelpsimproveitscodedensityoverthatofother8-bitters,accordingtoAtmel.ItsCPI（compareimmediate）instructionavoidstherelativelyawkwardconstructofloading,subtracting,andcheckingflagsusedonthe6805andPIC.Addingtwonumbersonthe8051,6805,orPICusuallyinvolvesshufflingbothoperandsthroughtheaccumulatorandstoringtheresult;AVRsimplyaddstworegisterswithoneinstructioninonecycle.

AVRisnotpureRISC-someinstructionsarelongerthanothers—norisitthefirst8-bitmicro-controllerwithabigregisterfile