中科院段成华专用集成电路设计作业4详解剖析.docx
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中科院段成华专用集成电路设计作业4详解剖析
Assignment4
1.Forthecascadedinverterpairshownbelow,usingHSPICEandTSMC0.18µmCMOStechnologymodelwith1.8VpowersupplyandassumingLn=200nm,Wn=400nm,ADn=0.2pm2,ASn=0.2pm2,Reqn=18KΩfortheNMOSdeviceandLp=200nm,Wp=800nm,ADp=0.4pm2,ASp=0.4pm2,Reqp=45KΩforthePMOSdevice,CW=0.01fF,please
（1）measuretheparasiticcapacitances:
Cdg1,Cdg2,Cdb1,Cdb2,Cg3,andCg4byHSPICEsimulation;
（2）accordingtothevaluesofthesecapacitances,computethepropagationdelays:
tPLH,tPHL,andtPDrespectively;
（3）measurethepropagationdelaytPDbyHSPICEsimulation,andcomparethevaluewiththeonejustcomputedfrom
（2）.
（Hint:
FordetailsofhowtomeasuretheparasiticcapacitancesofMOSFETdevicesinHSPICE,pleaserefertothe“MOSFETCapacitanceModels”sectionoftheHSPICEReferenceManual:
MOSFETModels,versionA-2007.09,Sept.2007,Synopsys.）
Solution:
（1）Codes
$Thecascadedinverterparasiticcapacitancescalculation
.lib'D:
\ProgramFiles（x86）\synopsys\Hspice_D-2010.03-SP1\MM018.L'TT*Set0.18umlibrary
*mndg0bNCHl=0.2uw=0.4uad=0.2e-12pd=0.4uas=0.2e-12ps=0.4u
*mndg0bNCHl=0.2uw=0.4uad=0.2e-12pd=1.4uas=0.2e-12ps=1.4u*three-side
vddvdd01.8
*vinn100.9pulse0.11.7150p50p50p200p600p
*vinn100.9pulse0.01.8150p5p5p290p600p
*m1n2n1vddvddPCHl=0.2uw=0.8uad=0.4p^2pd=0.8uas=0.4p^2ps=0.8u
m1n2n1vddvddPCHl=0.2uw=0.8uad=0.4e-12pd=0.8uas=0.4e-12ps=0.8u
*m2n2n100NCHl=0.2uw=0.4uad=0.2p^2pd=0.4uas=0.2p^2ps=0.4u
m2n2n100NCHl=0.2uw=0.4uad=0.2e-12pd=0.4uas=0.2e-12ps=0.4u
m3n3n2vddvddPCHl=0.2uw=0.8uad=0.4p^2pd=0.8uas=0.4p^2ps=0.8u
m4n3n200NCHl=0.2uw=0.4uad=0.2p^2pd=0.4uas=0.2p^2ps=0.4u
c1n200.01f
*c2n300.01f
*vdd01.8
vinn101.8ac.1
*vbb00
.acdec11.59155e61.59155e7
*Performafrequencysweepby1-pointperdecadefrom1.59to15.9MHz
.printCGD1=par（'-lx19（m2）'）CGD2=par（'-lx19（m1）'）CDB1=par（'-lx22（m2）'）
+CDB2=par（'-lx22（m1）'）CG3=lx18（m4）CG4=lx18（m3）
*CGGn=lx18（mn）=cgtot=cgs+cgd+cgb,
*CDDn=lx33（mn）=cdtot=cgd+cdb,
*CGDn=par（'-lx19（mn）'）=cgd,
*CDGn=par（'-lx32（mn）'）=cdg,
*CDBn=par（'-lx22（mn）'）=cdb
*CSS,CBBarenotprintedoutbecauseSourceandBulkaregrounded.
.printig_imag=ii2（mn）id_imag=ii1（mn）
*ii（mn）printstheimaginarypartofthecurrentthroughmn.
*first“i”:
current;second“i”:
imaginary
*ig_imag:
imaginarygatecurrent;id_imag:
imaginarydraincurrent
.alter
*vgg01.8
vinin00ac.1
.end
Results:
图1仿真的寄生电容值
图2仿真的寄生电容图示
（2）由
（1）中所得的电容值可得
CL=Cdg1+Cdg2+Cdb1+Cdb2+Cg3+Cg4+Cw=3.75fF
tPHL=0.69*Reqn*CL=0.69*（18/（400/200））
*3.75fF
23.29ps
tPLH=0.69*Reqp*CL=0.69*（45/（800/200））
*3.75fF
29.11ps
tPD=（1/2）*（tPHL+tPLH）=26.20ps
（3）Codes
$Bsim3demo3-themeasurestatementforinverter
.tran5p2000p
.lib'D:
\ProgramFiles（x86）\synopsys\Hspice_D-2010.03-SP1\MM018.L'TT*SetTSMC0.18umlibrary
*.modelpchPMOSlevel=49version=3.1
*.modelnchNMOSlevel=49version=3.1
.optionslistnodepostmeasout
*OptionList:
Printsalistofnetlistelements,nodeconnections,andvaluesforcomponents,voltageandcurrentsources,parameters,andmore.
*OptionNode:
Printsanodecross-referencetable.
*OptionPost:
Savessimulationresultsforviewingbyaninteractivewaveformviewer.
*OptionMeasout:
Outputs.MEASUREstatementvaluesandsweepparametersintoanASCIIfile.
vddvdd01.8
*vinn100.9pulse0.11.7150p50p50p200p600p
vinn100.9pulse0.01.8150p5p5p290p600p
*m1n2n1vddvddPCHl=0.2uw=0.8uad=0.4p^2pd=0.8uas=0.4p^2ps=0.8u
m1n2n1vddvddPCHl=0.2uw=0.8uad=0.4e-12pd=0.8uas=0.4e-12ps=0.8u
*m2n2n100NCHl=0.2uw=0.4uad=0.2p^2pd=0.4uas=0.2p^2ps=0.4u
m2n2n100NCHl=0.2uw=0.4uad=0.2e-12pd=0.4uas=0.2e-12ps=0.4u
m3n3n2vddvddPCHl=0.2uw=0.8uad=0.4p^2pd=0.8uas=0.4p^2ps=0.8u
m4n3n200NCHl=0.2uw=0.4uad=0.2p^2pd=0.4uas=0.2p^2ps=0.4u
c1n200.01f
*c2n300.01f
.paramtdval=50ptstop=2000p
.meastrantphltrigv（n1）val=0.9td=tdvalrise=2
+targv（n2）val=0.9fall=2
*rise=2specifiestomeasurethev（n1）voltageonlyonthefirsttworisingedgesofthewaveform.
*trigv（n1）val=0.9indicatestotriggerwhenthevoltageontherisingedgevoltageis0.9.
*td=tdval:
timeatwhichmeasurementstarts.
*tphlistheuser-definedvariablenameforthemeasurement（thetimedifferencebetweenTRIGandTARGevents）.
.meastrantplhtrigv（n1）val=0.9td=tdvalfall=2
+targv（n2）val=0.9rise=2
.meastranvmaxmaxv（n2）from=tdvalto=tstop
.meastranvminminv（n2）from=tdvalto=tstop
.meastrantrisetrigv（n2）val='vmin+.1*vmax'td=tdval
+rise=1targv（n2）val='.9*vmax'rise=1
.meastrantfalltrigv（n2）val='.9*vmax'td=tdval
+fall=2targv（n2）val='vmin+.1*vmax'fall=2
.printtranv（n1）v（n2）v（n3）
.end
Results:
图3仿真延时值
a）仿真所得输入输出
b）tPHL（约为19ps）放大后
c）tPLH（约为26ps）放大后
图4仿真延时示意图
由上图的结果可以看出
tPD=（1/2）*（tPHL+tPLH）=22.53ps
（2）和（3）对比可知，两者仅相差，3.67ps.
2.Thefollowingfigureshowsamaster-slavepositiveedge-triggeredd-flip-flop.Themasterandslavelatchesaretransparent.ByusingHSPICEcircuitsimulationtoolwiththetsmc0.18μmCMOStechnologylibrary,please
（1）measurethetimingparametersoftSETUP,tCOandtHOLD;
（2）accordingtotheresultsof
（1）,verifyifthetheoreticalequationstSETUP=3tP_INV+tP_TX,tCO=tP_INV+tP_TX,andtHOLD=0aresatisfied.
Solution
（1）Code
*bsim3dlatch.sp---cmosd-flip-flop,transparent
.lib'D:
\ProgramFiles（x86）\synopsys\Hspice_D-2010.03-SP1\MM018.L'TT*SetTSMC0.18umlibrary
.optionlistnodepost
.tran50p6000p
*Startsatransientanalysisthatsimulatesacircuitataspecifictime.
*format:
.TRANtstep1tstop1
.probetran
+clock=par（'v（clck）'）
+data=par（'v（d）'）
+q=par（'v（q）'）
*Usethiscommandtosaveoutputvariablestointerfaceandgraphdata
*files.Theparametercanbeanodevoltageorareasonableexpression.
.icv（q）=0$setinitialvalue.
*Thenodevoltagesthatyouspecifyinthe.ICstatementarefixedto
*determinetheDCoperatingpoint.Theyareusedonlyinthefirst
*iterationtosetaninitialguessfortheDCoperatingpointanalysis.
*waveforms
vdatadgndpulse（0,1.8200p,40p,40p1100p,2400p）
*pulse（v1v2tdtrtfpwper）
vclkclckgndpulse（0,1.8300p,40p,40p600p,1200p）
vclknclckngndpulse（1.8,0300p,40p,40p600p,1200p）
*
*top:
d-latch
*xclkinvclckclckninv$enableifasymmetric（overlapping）positive
*andnegativeclocksareused
xdlatchdclckclcknqqbdlatch
cwqgnd.1f$addwiredelay
*
xdlatch1qbclckclcknq1qb1dlatch1
cw1q1gnd.1f$addwiredelay
*
*macrodefinitions
*
**********************************
*
*n-channelmosfet
*
*draingatesource
.subcktnmosn1n2n3
mnn1n2n3gndNCHl=0.2uw=0.4uad=0.2p^2pd=0.4uas=0.2p^2ps=0.4u
.endsnmos
*
*p-channelmosfet
*
*draingatesource
.subcktpmosn1n2n3
vccvccgnd1.8
mpn1n2n3vccPCHl=0.2uw=0.8uad=0.4p^2pd=0.8uas=0.4p^2ps=0.8u
.endspmos
*
.subckttgateinoutclkclkn
xmninclkoutnmos
xmpinclknoutpmos
.endstgate
*
.subcktinvinout
vccvccgnd1.8
xmnoutingndnmos
xmpoutinvccpmos
.endsinv
*
.subcktdlatchdataclckclcknqqb
xtg1databaclckclckntgate
xtg2qaxclcknclcktgate
rxaxa5
xinv1aqbinv
xinv2qbqinv
xinv3datadatabinv
.endsdlatch
*
*.plotv（xdlatch.xinv1.out）
*.end
.subckttgate1inoutclkclkn
xmninclknoutnmos
xmpinclkoutpmos
.endstgate1
*
*
.subcktdlatch1qbclckclcknq1qb1
xtg3datab1a1clckclckntgate1
xtg4q1ax1clcknclcktgate1
rx1ax1a15
xinv4a1qb1inv
xinv5qb1q1inv
xinv6qbdatab1inv
.endsdlatch1
*
.plotv（xdlatch1.xinv6.out）
.end
Result
a）
b）
图5触发器仿真图
由上图中的点可以得知：
tSETUP=3.20e（-10）-2.20e（-10）=1.00e（-10）=100ps
tCO=2.24e（-9）-2.16e（-9）=0.08e（-9）=80ps
tHOLD=0ps
（2）由第一题可知：
tP_INV=22.53ps，对程序修改得tP_TX=46.40ps，根据上述公式得，tSETUP=3tP_INV+tP_TX=114ps，tCO=tP_INV+tP_TX=68.93ps，tHOLD=0，对比
（1）可知，在误差允许的范围内。
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