VHDL数字钟代码.docx
《VHDL数字钟代码.docx》由会员分享，可在线阅读，更多相关《VHDL数字钟代码.docx（28页珍藏版）》请在冰点文库上搜索。
VHDL数字钟代码
useieee.std_logic_1164.all;--顶层实体，用的是20Mhz的时钟
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entityclock_shuis
port（
clk:
instd_logic;
reset:
instd_logic;
duan:
outstd_logic_vector（5downto0）;
data_o:
outstd_logic_vector（7downto0）
）;
end;
architectureaofclock_shuis
componentcount60
port（
carry:
std_logic;
rst:
std_logic;
times:
outintegerrange0to59;
full:
outstd_logic
）;
endcomponent;
componentcount24
port（
carry:
instd_logic;
rst:
instd_logic;
times:
outintegerrange0to23
--full:
outstd_logic
）;
endcomponent;
componenti60bcd
port（
interg:
inintegerrange0to59;
ten:
outstd_logic_vector（7downto0）;
one:
outstd_logic_vector（7downto0）
）;
endcomponent;
componenti24bcd
port（
interg:
inintegerrange0to23;
ten:
outstd_logic_vector（7downto0）;
one:
outstd_logic_vector（7downto0）
）;
endcomponent;
signalcarry1,carry2:
std_logic;
signalabin1,abin2:
integerrange0to59;
signalabin3:
integerrange0to23;
signalclk_1h:
std_logic;
signalsh,sl,mh,ml,hh,hl:
std_logic_vector（7downto0）;
signalcnt:
integerrange0to5:
=0;
begin
process（clk）--分频为1hz
constantcounter_len:
integer:
=19999999;
variablecnt:
integerrange0tocounter_len;
begin
ifclk'eventandclk='1'then
ifcnt=counter_lenthen
cnt:
=0;
else
cnt:
=cnt+1;
endif;
casecntis
when0tocounter_len/2=>clk_1h<='0';
whenothers=>clk_1h<='1';
endcase;
endif;
endprocess;
process（clk）
variablecnt1:
integerrange0to200;
variablecnt2:
integerrange0to10;
begin
ifclk'eventandclk='1'then
ifcnt1=200then
cnt1:
=0;
ifcnt2=10then
cnt2:
=0;
if（cnt=5）then
cnt<=0;
else
cnt<=cnt+1;
endif;
else
cnt2:
=cnt2+1;
endif;
else
cnt1:
=cnt1+1;
endif;
endif;
endprocess;
process（clk）
begin
ifclk='1'then
casecntis
when0=>duan<="000001";data_o<=sl;
when1=>duan<="000010";data_o<=sh;
when2=>duan<="000100";data_o<=ml;
when3=>duan<="001000";data_o<=mh;
when4=>duan<="010000";data_o<=hl;
when5=>duan<="100000";data_o<=hh;
whenothers=>duan<="000000";
endcase;
endif;
endprocess;
u1:
count60portmap（carry=>clk_1h,rst=>reset,times=>abin1,full=>carry1）;
u2:
count60portmap（carry=>carry1,rst=>reset,times=>abin2,full=>carry2）;
u3:
count24portmap（carry=>carry2,rst=>reset,times=>abin3）;
u4:
i60bcdportmap（interg=>abin1,ten=>sh,one=>sl）;
u5:
i60bcdportmap（interg=>abin2,ten=>mh,one=>ml）;
u6:
i24bcdportmap（interg=>abin3,ten=>hh,one=>hl）;
end;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entitycount60is--分，秒计数器
port（
carry:
std_logic;
rst:
std_logic;
times:
outintegerrange0to59;
full:
outstd_logic
）;
end;
architectureaofcount60is
signaltime_s:
integerrange0to59;
begin
process（rst,carry）
begin
ifrst='1'then
time_s<=0;
full<='0';
elsifrising_edge（carry）then
iftime_s=59then
time_s<=0;
full<='1';
else
time_s<=time_s+1;
full<='0';
endif;
endif;
endprocess;
times<=time_s;
end;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entitycount24is--时计数器
port（
carry:
instd_logic;
rst:
instd_logic;
times:
outintegerrange0to23
--full:
outstd_logic
）;
end;
architectureaofcount24is
signaltime_s:
integerrange0to23;
begin
process（rst,carry）
begin
ifrst='1'then
time_s<=0;
--full<='0';
elsifrising_edge（carry）then
iftime_s=23then
time_s<=0;
--full<='1';
else
time_s<=time_s+1;
--full<='1';
endif;
endif;
endprocess;
times<=time_s;
end;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entityi60bcdis--分，秒显示
port（
interg:
inintegerrange0to59;
ten:
outstd_logic_vector（7downto0）;
one:
outstd_logic_vector（7downto0）
）;
end;
architectureaofi60bcdis
begin
process（interg）
begin
caseintergis
when0|10|20|30|40|50=>one<="11000000";
when1|11|21|31|41|51=>one<="11111001";
when2|12|22|32|42|52=>one<="10100100";
when3|13|23|33|43|53=>one<="10110000";
when4|14|24|34|44|54=>one<="10011001";
when5|15|25|35|45|55=>one<="10010010";
when6|16|26|36|46|56=>one<="10000011";
when7|17|27|37|47|57=>one<="11111000";
when8|18|28|38|48|58=>one<="10000000";
when9|19|29|39|49|59=>one<="10011000";
whenothers=>one<=null;
endcase;
caseintergis
when0|1|2|3|4|5|6|7|8|9=>ten<="11000000";
when10|11|12|13|14|15|16|17|18|19=>ten<="11111001";
when20|21|22|23|24|25|26|27|28|29=>ten<="10100100";
when30|31|32|33|34|35|36|37|38|39=>ten<="10110000";
when40|41|42|43|44|45|46|47|48|49=>ten<="10011001";
when50|51|52|53|54|55|56|57|58|59=>ten<="10010010";
whenothers=>ten<=null;
endcase;
endprocess;
end;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entityi24bcdis--时显示
port（
interg:
inintegerrange0to23;
ten:
outstd_logic_vector（7downto0）;
one:
outstd_logic_vector（7downto0）
）;
end;
architectureaofi24bcdis
begin
process（interg）
begin
caseintergis
when0|10|20=>one<="11000000";
when1|11|21=>one<="11111001";
when2|12|22=>one<="10100100";
when3|13|23=>one<="10110000";
when4|14=>one<="10011001";
when5|15=>one<="10010010";
when6|16=>one<="10000011";
when7|17=>one<="11111000";
when8|18=>one<="10000000";
when9|19=>one<="10011000";
whenothers=>one<=null;
endcase;
caseintergis
when0|1|2|3|4|5|6|7|8|9=>ten<="11000000";
when10|11|12|13|14|15|16|17|18|19=>ten<="11111001";
when20|21|22|23=>ten<="10100100";
whenothers=>ten<=null;
endcase;
endprocess;
end;
回答者：
ail傻大个|三级|2010-12-2917:
19
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityMINSECONDbis
port（clk,clrm,stop:
instd_logic;----时钟/清零信号
secm1,secm0:
outstd_logic_vector（3downto0）;----秒高位/低位
co:
outstd_logic）;-------输出/进位信号
endMINSECONDb;
architectureSECofMINSECONDbis
signalclk1,DOUT2:
std_logic;
begin
process（clk,clrm）
variablecnt1,cnt0:
std_logic_vector（3downto0）;---计数
VARIABLECOUNT2:
INTEGERRANGE0TO10;
begin
IFCLK'EVENTANDCLK='1'THEN
IFCOUNT2>=0ANDCOUNT2<10THEN
COUNT2:
=COUNT2+1;
ELSECOUNT2:
=0;
DOUT2<=NOTDOUT2;
ENDIF;
ENDIF;
ifclrm='1'then----当clr为1时，高低位均为0
cnt1:
="0000";
cnt0:
="0000";
elsifclk'eventandclk='1'then
ifstop='1'then
cnt0:
=cnt0;
cnt1:
=cnt1;
endif;
ifcnt1="1001"andcnt0="1000"then----当记数为98（实际是经过59个记时脉冲）
co<='1';----进位
cnt0:
="1001";----低位为9
elsifcnt0<"1001"then----小于9时
cnt0:
=cnt0+1;----计数
--elsifcnt0="1001"then
--clk1<=notclk1;
else
cnt0:
="0000";
ifcnt1<"1001"then----高位小于9时
cnt1:
=cnt1+1;
else
cnt1:
="0000";
co<='0';
endif;
endif;
endif;
secm1<=cnt1;
secm0<=cnt0;
endprocess;
endSEC;
秒模块程序清单
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitySECONDis
port（clk,clr:
instd_logic;----时钟/清零信号
sec1,sec0:
outstd_logic_vector（3downto0）;----秒高位/低位
co:
outstd_logic）;-------输出/进位信号
endSECOND;
architectureSECofSECONDis
begin
process（clk,clr）
variablecnt1,cnt0:
std_logic_vector（3downto0）;---计数
begin
ifclr='1'then----当ckr为1时，高低位均为0
cnt1:
="0000";
cnt0:
="0000";
elsifclk'eventandclk='1'then
ifcnt1="0101"andcnt0="1000"then----当记数为58（实际是经过59个记时脉冲）
co<='1';----进位
cnt0:
="1001";----低位为9
elsifcnt0<"1001"then----小于9时
cnt0:
=cnt0+1;----计数
else
cnt0:
="0000";
ifcnt1<"0101"then----高位小于5时
cnt1:
=cnt1+1;
else
cnt1:
="0000";
co<='0';
endif;
endif;
endif;
sec1<=cnt1;
sec0<=cnt0;
endprocess;
endSEC;
分模块程序清单
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityMINUTEis
port（clk,en:
instd_logic;
min1,min0:
outstd_logic_vector（3downto0）;
co:
outstd_logic）;
endMINUTE;
architectureMINofMINUTEis
begin
process（clk）
variablecnt1,cnt0:
std_logic_vector（3downto0）;
begin
ifclk'eventandclk='1'then
ifen='1'then
ifcnt1="0101"andcnt0="1000"then
co<='1';
cnt0:
="1001";
elsifcnt0<"1001"then
cnt0:
=cnt0+1;
else
cnt0:
="0000";
ifcnt1<"0101"then
cnt1:
=cnt1+1;
else
cnt1:
="0000";
co<='0';
endif;
endif;
endif;
endif;
min1<=cnt1;
min0<=cnt0;
endprocess;
endMIN;
时模块程序清单
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityHOURis
port（clk,en:
instd_logic;----输入时钟/高电平有效的使能信号
h1,h0:
outstd_logic_vector（3downto0））;----时高位/低位
endHOUR;
architecturehour_arcofHOURis
begin
process（clk）
variablecnt1,cnt0:
std_logic_vector（3downto0）;----记数
begin
ifclk'eventandclk='1'then---上升沿触发
ifen='1'then---同时“使能”为1
ifcnt1="0010"andcnt0="0011"then
cnt1:
="0000";----高位/低位同时为0时
cnt0:
="0000";
elsifcnt0<"1001"then----低位小于9时，低位记数累加
cnt0:
=cnt0+1;
else
cnt0:
="0000";
cnt1:
=cnt1+1;-----高位记数累加
endif;
endif;
endif;
h1<=cnt1;
h0<=cnt0;
endprocess;
endhour_arc;
动态扫描模块
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entitySELTIMEis
port（
clk:
instd_logic;------扫描时钟
secm1,secm0,sec1,sec0,min1,min0,h1,h0:
instd_logic_vector（3downto0）;-----分别为秒个位/时位；分个位/
daout:
outstd_logic_vector（3downto0）;----------------输出
sel:
outstd_logic_vector（2downto0））;-----位选信号
endSELTIME;
architecturefunofSELTIMEis
signalcount:
std_logic_vector（2downto0）;----计数信号
begin
sel<=count;
process（clk）
begin
if（clk'eventandclk='1'）then
if（count>="111"）then
count<="000";
else
count<=count+1;
endif;
endif;
case
升级会员 