西工大数电实验4.docx

西工大数电实验4.docx

《西工大数电实验4.docx》由会员分享，可在线阅读，更多相关《西工大数电实验4.docx（10页珍藏版）》请在冰点文库上搜索。

西工大数电实验4

实验四：

基于quartusII的计时电路设计

一、实验目的

1.熟练掌握quartusII软件的使用，使用quartusII设计计时电路

2.通过对计时电路的设计熟练掌握与巩固之前学习的内容，并加深对于数电这门学科的了解与认识。

二、实验设备

1.计算机及quartusII软件

2.数字电路实验箱

3.实验开发板DE0

三、实验内容

顶层电路设计采用原理图输入方法，各电路模块可以采用原理图或硬件描述语言输入方法实现一个简易计时电路。

基本要求：

由四个数码管显示的计时电路，低两位按照20进制设计，高两位按照11进制设计。

附加要求

1：

该计时电路具有校准功能,可以按1Hz频率校准高两位的显示,可以按10Hz频率校准低两位的显示；

2：

高两位的进制可以任意设置。

（不需要从新编译电路）

3：

在计数到达某整点值时例如0300的时刻（该值可以根据老师的要求设置）,4盏LED灯一起按照10Hz闪烁5秒钟。

四、实验过程

原理图

exa4_1输出频率1Hz

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

ENTITYexa4_1IS

PORT（clk:

INSTD_LOGIC;

clk_out:

OUTSTD_LOGIC）;

ENDexa4_1;

ARCHITECTUREfwmOFexa4_1IS

CONSTANTm:

INTEGER:

=25000000;

SIGNALtmp:

STD_LOGIC;

BEGIN

PROCESS（clk,tmp）

VARIABLEcout:

INTEGER:

=0;

BEGIN

IFclk'EVENTANDclk='1'THEN

cout:

=cout+1;

IFcout<=mTHENtmp<='0';

ELSIFcout

ELSEcout:

=0;

ENDIF;

ENDIF;

ENDPROCESS;

clk_out<=tmp;

ENDfwm;

exa4_2输出频率10Hz

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

ENTITYexa4_2IS

PORT（clk:

INSTD_LOGIC;

clk_out:

OUTSTD_LOGIC）;

ENDexa4_2;

ARCHITECTUREfwmOFexa4_2IS

CONSTANTm:

INTEGER:

=2500000;

SIGNALtmp:

STD_LOGIC;

BEGIN

PROCESS（clk,tmp）

VARIABLEcout:

INTEGER:

=0;

BEGIN

IFclk'EVENTANDclk='1'THEN

cout:

=cout+1;

IFcout<=mTHENtmp<='0';

ELSIFcout

ELSEcout:

=0;

ENDIF;

ENDIF;

ENDPROCESS;

clk_out<=tmp;

ENDfwm;

exa4_311进制加法计数器

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYexa4_3IS

PORT（CLK,RST:

INSTD_LOGIC;

DOUT:

OUTSTD_LOGIC_VECTOR（3DOWNTO0））;

ENDexa4_3;

ARCHITECTUREfwmOFexa4_3IS

SIGNALQ1:

STD_LOGIC_VECTOR（3DOWNTO0）;

BEGIN

PROCESS（CLK,RST）

BEGIN

IFRST='0'THENQ1<=（OTHERS=>'0'）;

ELSIFRISING_EDGE（clk）THEN

IFQ1<"1010"THENQ1<=Q1+1;

ELSEQ1<=（OTHERS=>'0'）;

ENDIF;

ENDIF;

ENDPROCESS;

DOUT<=Q1;

ENDfwm;

exa4_420进制加法计数器

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYexa4_4IS

PORT（CLK,RST:

INSTD_LOGIC;

DOUT:

OUTSTD_LOGIC_VECTOR（4DOWNTO0））;

ENDexa4_4;

ARCHITECTUREfwmOFexa4_4IS

SIGNALQ1:

STD_LOGIC_VECTOR（4DOWNTO0）;

BEGIN

PROCESS（CLK,RST）

BEGIN

IFRST='0'THENQ1<=（OTHERS=>'0'）;

ELSIFRISING_EDGE（clk）THEN

IFQ1<"10011"THENQ1<=Q1+1;

ELSEQ1<=（OTHERS=>'0'）;

ENDIF;

ENDIF;

ENDPROCESS;

DOUT<=Q1;

ENDfwm;

exa4_511进制的个位显示

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

ENTITYexa4_5IS

PORT（data_in:

INSTD_LOGIC_VECTOR（3DOWNTO0）;

dis_out:

OUTSTD_LOGIC_VECTOR（6DOWNTO0））;

ENDexa4_5;

ARCHITECTUREfwmOFexa4_5IS

BEGIN

PROCESS（data_in）

BEGIN

CASEdata_inIS

WHEN"0000"=>dis_out<="1000000";

WHEN"0001"=>dis_out<="1111001";

WHEN"0010"=>dis_out<="0100100";

WHEN"0011"=>dis_out<="0110000";

WHEN"0100"=>dis_out<="0011001";

WHEN"0101"=>dis_out<="0010010";

WHEN"0110"=>dis_out<="0000010";

WHEN"0111"=>dis_out<="1111000";

WHEN"1000"=>dis_out<="0000000";

WHEN"1001"=>dis_out<="0010000";

WHEN"1010"=>dis_out<="1000000";

WHENOTHERS=>dis_out<="1111111";

ENDCASE;

ENDPROCESS;

ENDfwm;

exa4_611进制的十位显示

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

ENTITYexa4_6IS

PORT（data_in:

INSTD_LOGIC_VECTOR（3DOWNTO0）;

dis_out:

OUTSTD_LOGIC_VECTOR（6DOWNTO0））;

ENDexa4_6;

ARCHITECTUREfwmOFexa4_6IS

BEGIN

PROCESS（data_in）

BEGIN

CASEdata_inIS

WHEN"0000"=>dis_out<="1000000";

WHEN"0001"=>dis_out<="1000000";

WHEN"0010"=>dis_out<="1000000";

WHEN"0011"=>dis_out<="1000000";

WHEN"0100"=>dis_out<="1000000";

WHEN"0101"=>dis_out<="1000000";

WHEN"0110"=>dis_out<="1000000";

WHEN"0111"=>dis_out<="1000000";

WHEN"1000"=>dis_out<="1000000";

WHEN"1001"=>dis_out<="1000000";

WHEN"1010"=>dis_out<="1111001";

WHENOTHERS=>dis_out<="1111111";

ENDCASE;

ENDPROCESS;

ENDfwm;

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

exa4_720进制的个位显示

ENTITYexa4_7IS

PORT（data_in:

INSTD_LOGIC_VECTOR（4DOWNTO0）;

dis_out:

OUTSTD_LOGIC_VECTOR（6DOWNTO0））;

ENDexa4_7;

ARCHITECTUREfwmOFexa4_7IS

BEGIN

PROCESS（data_in）

BEGIN

CASEdata_inIS

WHEN"00000"=>dis_out<="1000000";

WHEN"00001"=>dis_out<="1111001";

WHEN"00010"=>dis_out<="0100100";

WHEN"00011"=>dis_out<="0110000";

WHEN"00100"=>dis_out<="0011001";

WHEN"00101"=>dis_out<="0010010";

WHEN"00110"=>dis_out<="0000010";

WHEN"00111"=>dis_out<="1111000";

WHEN"01000"=>dis_out<="0000000";

WHEN"01001"=>dis_out<="0010000";

WHEN"01010"=>dis_out<="1000000";

WHEN"01011"=>dis_out<="1111001";

WHEN"01100"=>dis_out<="0100100";

WHEN"01101"=>dis_out<="0110000";

WHEN"01110"=>dis_out<="0011001";

WHEN"01111"=>dis_out<="0010010";

WHEN"10000"=>dis_out<="0000010";

WHEN"10001"=>dis_out<="1111000";

WHEN"10010"=>dis_out<="0000000";

WHEN"10011"=>dis_out<="0010000";

WHENOTHERS=>dis_out<="1111111";

ENDCASE;

ENDPROCESS;

ENDfwm;

exa4_820进制的十位显示

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

ENTITYexa4_8IS

PORT（data_in:

INSTD_LOGIC_VECTOR（4DOWNTO0）;

dis_out:

OUTSTD_LOGIC_VECTOR（6DOWNTO0））;

ENDexa4_8;

ARCHITECTUREfwmOFexa4_8IS

BEGIN

PROCESS（data_in）

BEGIN

CASEdata_inIS

WHEN"00000"=>dis_out<="1000000";

WHEN"00001"=>dis_out<="1000000";

WHEN"00010"=>dis_out<="1000000";

WHEN"00011"=>dis_out<="1000000";

WHEN"00100"=>dis_out<="1000000";

WHEN"00101"=>dis_out<="1000000";

WHEN"00110"=>dis_out<="1000000";

WHEN"00111"=>dis_out<="1000000";

WHEN"01000"=>dis_out<="1000000";

WHEN"01001"=>dis_out<="1000000";

WHEN"01010"=>dis_out<="1111001";

WHEN"01011"=>dis_out<="1111001";

WHEN"01100"=>dis_out<="1111001";

WHEN"01101"=>dis_out<="1111001";

WHEN"01110"=>dis_out<="1111001";

WHEN"01111"=>dis_out<="1111001";

WHEN"10000"=>dis_out<="1111001";

WHEN"10001"=>dis_out<="1111001";

WHEN"10010"=>dis_out<="1111001";

WHEN"10011"=>dis_out<="1111001";

WHENOTHERS=>dis_out<="1111111";

ENDCASE;

ENDPROCESS;

ENDfwm;