用verilog编写的8位扩展超前进位加法器代码.docx
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用verilog编写的8位扩展超前进位加法器代码
8位扩展超前进位加法器
/******************************************************************************
Ci+1=Ai*Bi+Bi*Ci+Ci*Ai
=Ai*Bi+（Ai+Bi）*Ci
Gi =Ai*Bi
Pi =Ai+Bi
Ci+1=Gi+Pi*Ci
=Gi+Pi*（Gi-1+Pi-1*Ci-1）
=Gi+Pi*（Gi-1+Pi-1*（Gi-2+Pi-2*Ci-2））
.
.
.
=Gi+Pi*（Gi-1+Pi-1*（Gi-2+Pi-2*（...（G0+P0*C0）...）））
=Gi+Pi*Gi-1+Pi*Pi-1*Gi-2+...+Pi*Pi-1*...*P1*G0
+Pi*Pi-1*...*P1*P0*C0
Gij =Gi+Pi*Gi-1+Pi*Pi-1*Gi-2+...+Pi*Pi-1*...*Pj+1*Gj
Pij =Pi*Pi-1*...*Pj+1*Pj;
Gi,i=Gi;
Pi,i=Pi;
******************************************************************************/
moduleadder_8bits（s,co,a,b,ci）;
output[7:
0]s;
outputco;
input [7:
0]a;
input [7:
0]b;
input ci;
wire [7:
0]g;
wire [7:
0]p;
wire [8:
0]c;
assigng=a&b;
assignp=a|b;
assigng00_00=g[0];
assignp00_00=p[0];
assigng02_02=g[2];
assignp02_02=p[2];
assigng04_04=g[4];
assignp04_04=p[4];
assigng06_06=g[6];
assignp06_06=p[6];
assigng01_00=g[1]|p[1]&g[0];
assignp01_00=p[1]&p[0];
assigng03_02=g[3]|p[3]&g[2];
assignp03_02=p[3]&p[2];
assigng03_00=g03_02|p03_02&g01_00;
assignp03_00=p03_02&p01_00;
assigng05_04=g[5]|p[5]&g[4];
assignp05_04=p[5]&p[4];
assigng07_06=g[7]|p[7]&g[6];
assignp07_06=p[7]&p[6];
assigng07_04=g07_06|p07_06&g05_04;
assignp07_04=p07_06&p05_04;
assigng07_00=g07_04|p07_04&g03_00;
assignp07_00=p07_04&p03_00;
assignc[0]=ci;
assignc[1]=g00_00|p00_00&c[0];
assignc[2]=g01_00|p01_00&c[0];
assignc[3]=g02_02|p02_02&c[2];
assignc[4]=g03_00|p03_00&c[0];
assignc[5]=g04_04|p04_04&c[4];
assignc[6]=g05_04|p05_04&c[4];
assignc[7]=g06_06|p06_06&c[6];
assignc[8]=g07_00|p07_00&c[0];
assignco =c[8];
assigns=a^b^c[7:
0];
endmodule
moduletest;
regclk;
reg[7:
0]a;
reg[7:
0]b;
regci;
wire[7:
0]s;
initialbegin
clk=0;
ci =1;
a=8'b0000_0000;
b=8'b0000_0000;
#10000$stop;
end
always#5clk<=~clk;
always@（posedgeclk）begin
a<=a+8'b0000_0001;
end
always@（negedgeclk）begin
b<=b+8'b0000_0001;
end
adder_8bitsu（.s（s）,.co（co）,.a（a）,.b（b）,.ci（ci））;
endmodule
32bitsadder 上一篇 下一篇
发布者：
syinspire|发表时间：
2007-01-2521:
37 |标签：
32 bits adder
/******************************************************************************
Ci+1=Ai*Bi+Bi*Ci+Ci*Ai
=Ai*Bi+（Ai+Bi）*Ci
Gi =Ai*Bi
Pi =Ai+Bi
Ci+1=Gi+Pi*Ci
=Gi+Pi*（Gi-1+Pi-1*Ci-1）
=Gi+Pi*（Gi-1+Pi-1*（Gi-2+Pi-2*Ci-2））
.
.
.
=Gi+Pi*（Gi-1+Pi-1*（Gi-2+Pi-2*（...（G0+P0*C0）...）））
=Gi+Pi*Gi-1+Pi*Pi-1*Gi-2+...+Pi*Pi-1*...*P1*G0
+Pi*Pi-1*...*P1*P0*C0
Gij =Gi+Pi*Gi-1+Pi*Pi-1*Gi-2+...+Pi*Pi-1*...*Pj+1*Gj
Pij =Pi*Pi-1*...*Pj+1*Pj;
Gij =Gik+Pik*Gk-1j
Pij =Pik*Pkj
Ci+1=Gij+Pij*Cj
Gi,i=Gi;
Pi,i=Pi;
******************************************************************************/
moduleadder_32bits（s,co,a,b,ci）;
output[31:
0]s;
outputco;
input [31:
0]a;
input [31:
0]b;
input ci;
wire [31:
0]g;
wire [31:
0]p;
wire [32:
0]c;
assigng=a&b;
assignp=a|b;
assigng00_00=g[0];
assignp00_00=p[0];
assigng02_02=g[2];
assignp02_02=p[2];
assigng04_04=g[4];
assignp04_04=p[4];
assigng06_06=g[6];
assignp06_06=p[6];
assigng08_08=g[8];
assignp08_08=p[8];
assigng10_10=g[10];
assignp10_10=p[10];
assigng12_12=g[12];
assignp12_12=p[12];
assigng14_14=g[14];
assignp14_14=p[14];
assigng16_16=g[16];
assignp16_16=p[16];
assigng18_18=g[18];
assignp18_18=p[18];
assigng20_20=g[20];
assignp20_20=p[20];
assigng22_22=g[22];
assignp22_22=p[22];
assigng24_24=g[24];
assignp24_24=p[24];
assigng26_26=g[26];
assignp26_26=p[26];
assigng28_28=g[28];
assignp28_28=p[28];
assigng30_30=g[30];
assignp30_30=p[30];
assigng01_00=g[1]|p[1]&g[0];
assignp01_00=p[1]&p[0];
assigng03_02=g[3]|p[3]&g[2];
assignp03_02=p[3]&p[2];
assigng03_00=g03_02|p03_02&g01_00;
assignp03_00=p03_02&p01_00;
assigng05_04=g[5]|p[5]&g[4];
assignp05_04=p[5]&p[4];
assigng07_06=g[7]|p[7]&g[6];
assignp07_06=p[7]&p[6];
assigng07_04=g07_06|p07_06&g05_04;
assignp07_04=p07_06&p05_04;
assigng07_00=g07_04|p07_04&g03_00;
assignp07_00=p07_04&p03_00;
assigng09_08=g[9]|p[9]&g[8];
assignp09_08=p[9]&p[8];
assigng11_10=g[11]|p[11]&g[10];
assignp11_10=p[11]&p[11];
assigng11_08=g11_10|p11_10&g09_08;
assignp11_08=p11_10&p09_08;
assigng13_12=g[13]|p[13]&g[12];
assignp13_12=p[13]&p[12];
assigng15_14=g[15]|p[15]&g[14];
assignp15_14=p[15]&p[14];
assigng15_12=g15_14|p15_14&g13_12;
assignp15_12=p15_14&p13_12;
assigng15_08=g15_12|p15_12&g11_08;
assignp15_08=p15_12&p11_08;
assigng15_00=g15_08|p15_08&g07_00;
assignp15_00=p15_08&p07_00;
assigng17_16=g[17]|p[17]&g[16];
assignp17_16=p[17]&p[16];
assigng19_18=g[19]|p[19]&g[18];
assignp19_18=p[19]&p[18];
assigng19_16=g19_18|p19_18&g17_16;
assignp19_16=p19_18&p17_16;
assigng21_20=g[21]|p[21]&g[20];
assignp21_20=p[21]&p[20];
assigng23_22=g[23]|p[23]&g[22];
assignp23_22=p[23]&p[22];
assigng23_20=g23_22|p23_22&g21_20;
assignp23_20=p23_22&p21_20;
assigng23_16=g23_20|p23_20&g19_16;
assignp23_16=p23_20&p19_16;
assigng25_24=g[25]|p[25]&g[24];
assignp25_24=p[25]&p[24];
assigng27_26=g[27]|p[27]&g[26];
assignp27_26=p[27]&p[26];
assigng27_24=g27_26|p27_26&g25_24;
assignp27_24=p27_26&p25_24;
assigng29_28=g[29]|p[29]&g[28];
assignp29_28=p[29]&p[28];
assigng31_30=g[31]|p[31]&g[30];
assignp31_30=p[31]&p[30];
assigng31_28=g31_30|p31_30&g29_28;
assignp31_28=p31_30&p29_28;
assigng31_24=g31_28|p31_28&g27_24;
assignp31_24=p31_28&p27_24;
assigng31_16=g31_24|p31_24&g23_16;
assignp31_16=p31_24&p23_16;
assigng31_00=g31_16|p31_16&g15_00;
assignp31_00=p31_16&p15_00;
assignc[0] =ci;
assignc[1] =g00_00|p00_00&c[0];
assignc[2] =g01_00|p01_00&c[0];
assignc[3] =g02_02|p02_02&c[2];
assignc[4] =g03_00|p03_00&c[0];
assignc[5] =g04_04|p04_04&c[4];
assignc[6] =g05_04|p05_04&c[4];
assignc[7] =g06_06|p06_06&c[6];
assignc[8] =g07_00|p07_00&c[0];
assignc[9] =g08_08|p08_08&c[8];
assignc[10]=g09_08|p09_08&c[8];
assignc[11]=g10_10|p10_10&c[10];
assignc[12]=g11_08|p11_08&c[8];
assignc[13]=g12_12|p12_12&c[12];
assignc[14]=g13_12|p13_12&c[12];
assignc[15]=g14_14|p14_14&c[14];
assignc[16]=g15_00|p15_00&c[0];
assignc[17]=g16_16|p16_16&c[16];
assignc[18]=g17_16|p17_16&c[16];
assignc[19]=g18_18|p18_18&c[18];
assignc[20]=g19_16|p19_16&c[16];
assignc[21]=g20_20|p20_20&c[20];
assignc[22]=g21_20|p21_20&c[20];
assignc[23]=g22_22|p22_22&c[22];
assignc[24]=g23_16|p23_16&c[16];
assignc[25]=g24_24|p24_24&c[24];
assignc[26]=g25_24|p25_24&c[24];
assignc[27]=g26_26|p26_26&c[26];
assignc[28]=g27_24|p27_24&c[24];
assignc[29]=g28_28|p28_28&c[28];
assignc[30]=g29_28|p29_28&c[28];
assignc[31]=g30_30|p30_30&c[30];
assignc[32]=g31_00|p31_00&c[0];
assignco =c[32];
assigns=a^b^c[31:
0];
endmodule
moduletest;
regclk;
reg[31:
0]a;
reg[31:
0]b;
regci;
wire[31:
0]s;
initialbegin
clk=0;
ci =1;
a=32'h0000_0001;
b=32'h0000_0001;
#4294967200$stop;
end
always#0.5clk<=~clk;
always@（posedgeclk）begin
a<=a+32'h0000_0001;
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