CPLD数字时钟.docx
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CPLD数字时钟
CPLD大作业(2007.6.28)
题目:
设计数字钟,要求数字钟的秒针部分由50进制计数器组成,分针部亦由50进制计数器组成,时钟部分为24进制组成。
根据题意可有两种设计方案,一种是由一个模块实现的数字钟,另一种是由三个模块实现的数字钟。
1.一个模块实现的数字钟设计方案
1)程序
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYclk11IS
PORT(
CLRN,LDN,EN,CLK:
INSTD_LOGIC;
Sa,Ma,Ha:
ININTEGERRANGE0TO9;
Sb,Mb:
ININTEGERRANGE0TO4;
Hb:
ININTEGERRANGE0TO2;
QSa,QMa,QHa:
OUTINTEGERRANGE0TO9;
QSb,QMb:
OUTINTEGERRANGE0TO4;
QHb:
OUTINTEGERRANGE0TO2
);
ENDclk11;
ARCHITECTUREaOFclk11IS
BEGIN
PROCESS(CLK)
VARIABLEtmpsa,tmpma,tmpha:
INTEGERRANGE0TO9;
VARIABLEtmpsb,tmpmb:
INTEGERRANGE0TO4;
VARIABLEtmphb:
INTEGERRANGE0TO2;
BEGIN
IFCLRN='0'THEN
tmpsb:
=0;tmpsa:
=0;
tmpmb:
=0;tmpma:
=0;
tmphb:
=0;tmpha:
=0;
ELSE
IF(CLK'eventANDCLK='1')THEN
IFLDN='0'THEN
tmpsa:
=Sa;tmpsb:
=Sb;tmpma:
=Ma;tmpmb:
=Mb;
tmpha:
=Ha;tmphb:
=Hb;
ELSIFEN='1'THEN
IF(tmpsb=4ANDtmpsa=9ANDtmpmb=4ANDtmpma=9)THEN
IF(tmphb=2ANDtmpha=3)THEN
tmpha:
=0;tmphb:
=0;
ELSIFtmpha=9THEN
tmpha:
=0;tmphb:
=tmphb+1;
ELSEtmpha:
=tmpha+1;
ENDIF;
ENDIF;
IF(tmpsb=4ANDtmpsa=9)THEN
IFtmpma=9THEN
tmpma:
=0;
IFtmpmb=4THENtmpmb:
=0;
ELSEtmpmb:
=tmpmb+1;
ENDIF;
ELSEtmpma:
=tmpma+1;
ENDIF;
ENDIF;
IFtmpsa=9THEN
tmpsa:
=0;
IFtmpsb=4THENtmpsb:
=0;
ELSEtmpsb:
=tmpsb+1;
ENDIF;
ELSEtmpsa:
=tmpsa+1;
ENDIF;
ENDIF;
ENDIF;
ENDIF;
QSa<=tmpsa;QSb<=tmpsb;
QMa<=tmpma;QMb<=tmpmb;
Qha<=tmpha;Qhb<=tmphb;
ENDPROCESS;
ENDa;
2)电路图
3)波形图
4)分析
从波形图可见当秒针计数器满50秒,有进位;当分针计数器满50分钟,有进位;当小时计数器满24小时,计数器清零,可见,达到了设计要求。
2.由三个模块实现的数字钟设计方案
1)程序
程序1(24小时计数器):
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYcout24_vIS
PORT(
CLRN,LDN,EN,CLK:
INSTD_LOGIC;
Da:
ININTEGERRANGE0TO9;
Db:
ININTEGERRANGE0TO9;
Qa:
OUTINTEGERRANGE0TO9;
Qb:
OUTINTEGERRANGE0TO2
);
ENDcout24_v;
ARCHITECTUREaOFcout24_vIS
BEGIN
PROCESS(Clk)
VARIABLEtmpa:
INTEGERRANGE0TO9;
VARIABLEtmpb:
INTEGERRANGE0TO9;
BEGIN
IFCLRN='0'THENtmpb:
=0;tmpa:
=0;
ELSE
IF(CLK'eventANDCLK='1')THEN
IFLDN='0'THEN
tmpa:
=Da;tmpb:
=Db;
ELSIFEN='1'THEN
IFtmpa=9THEN
tmpa:
=0;tmpb:
=tmpb+1;
ELSIF(tmpb=2ANDtmpa=3)THEN
tmpb:
=0;tmpa:
=0;
ELSEtmpa:
=tmpa+1;
ENDIF;
ENDIF;
ENDIF;
ENDIF;
Qa<=tmpa;Qb<=tmpb;
ENDPROCESS;
ENDa;
程序2(50进制计数器):
LIBRARYieee;
USEieee.std_logic_1164.all;
USEieee.std_logic_unsigned.all;
ENTITYcout50_v11IS
PORT(
CLRN,LDN,EN,CLK:
INSTD_LOGIC;
Da:
INSTD_LOGIC_VECTOR(3downto0);
Db:
INSTD_LOGIC_VECTOR(2downto0);
Qa:
OUTSTD_LOGIC_VECTOR(3downto0);
Qb:
OUTSTD_LOGIC_VECTOR(2downto0);
RCO:
OUTSTD_LOGIC
);
ENDcout50_v11;
ARCHITECTUREaOFcout50_v11IS
BEGIN
PROCESS(Clk)
VARIABLEtmpa:
STD_LOGIC_VECTOR(3downto0);
VARIABLEtmpb:
STD_LOGIC_VECTOR(2downto0);
BEGIN
IFCLRN='0'THENtmpb:
="000";tmpa:
="0000";
ELSEIF(Clk'eventANDClk='1')THEN
IFLDN='0'THENtmpa:
=Da;tmpb:
=Db;
ELSIFEN='1'THEN
IFtmpa="1001"THEN
tmpa:
="0000";
IFtmpb="100"THENtmpb:
="000";
ELSEtmpb:
=tmpb+1;
ENDIF;
ELSEtmpa:
=tmpa+1;
ENDIF;
ENDIF;
ENDIF;
ENDIF;
Qa<=tmpa;Qb<=tmpb;
RCO<=tmpb
(2)ANDtmpa(0)ANDtmpa(3)ANDEN;--十位为'100',即4,个位为'1001'即9时,执行进位
ENDPROCESS;
ENDa;
2)电路图
3)波形图
4)分析
从波形图可见当秒针计数器满50秒,有进位,即ARCO进位变高电平;当分针计数器满50分钟,有进位,即BRCO进位变高电平;当小时计数器满24小时,计数器清零,可见,达到了设计要求。