VHDL多功能数字钟实现程序Word文档下载推荐.docx

VHDL多功能数字钟实现程序Word文档下载推荐.docx

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signalnewday0:

signalnewday1:

procedureFeb_sub_day（oldday0,oldday1:

procedureoddmonth_add_day（oldday0,oldday1:

procedureoddmonth_sub_day（oldday0,oldday1:

procedureevenmonth_add_day（oldday0,oldday1:

procedureevenmonth_sub_day（oldday0,oldday1:

signalnewday0:

procedureaddsec_addmin（oldtime0,oldtime1:

signalnewtime0:

signalnewtime1:

proceduresubsec_submin（oldtime0,oldtime1:

procedureaddhour（oldhour0,oldhour1:

signalnewhour0:

signalnewhour1:

proceduresubhour（oldhour0,oldhour1:

endpac;

packagebodypacis

procedureadd_year（oldyear0,oldyear1:

outstd_logic_vector）is

begin

if（oldyear0="

1001"

andoldyear1/="

）then

newyear0<

="

0000"

;

newyear1<

=oldyear1+'

1'

elsenewyear0<

=oldyear0+'

endif;

andoldyear1="

endadd_year;

procedureadd_month（oldmonth0,oldmonth1:

if（oldmonth0="

0010"

andoldmonth1="

0001"

newmonth0<

newmonth1<

elsifoldmonth0="

then

newmonth0<

=oldmonth1+'

elsenewmonth0<

=oldmonth0+'

endadd_month;

proceduresub_year（oldyear0,oldyear1:

ifoldyear0="

ifoldyear1="

newyear1<

elsenewyear1<

=oldyear1-'

newyear0<

=oldyear0-'

endsub_year;

proceduresub_month（oldmonth0,oldmonth1:

elsif（oldmonth0="

=oldmonth1-'

=oldmonth0-'

endsub_month;

procedureFeb_add_day（oldday0,oldday1:

Ty1:

begin--平年2月天数加

if（oldday0="

1000"

andoldday1="

）then

if（（Ty1='

0'

andTy0="

00"

）or（Ty1='

10"

））then

newday0<

=oldday0+'

else

newday1<

elsif（oldday0="

=oldday1+'

elsenewday0<

endFeb_add_day;

procedureFeb_sub_day（oldday0,oldday1:

begin--平年2月减

oroldday0="

）andoldday1="

））then

elsif（oldday0="

andoldday1/="

=oldday1-'

=oldday0-'

endFeb_sub_day;

procedureoddmonth_add_day（oldday0,oldday1:

begin--大月加

0011"

elsifoldday0="

endoddmonth_add_day;

procedureoddmonth_sub_day（oldday0,oldday1:

begin--大月减

then

endoddmonth_sub_day;

procedureevenmonth_add_day（oldday0,oldday1:

begin--小月加

endevenmonth_add_day;

procedureevenmonth_sub_day（oldday0,oldday1:

begin--小月减

endevenmonth_sub_day;

procedureaddsec_addmin（oldtime0,oldtime1:

begin--秒、分加

if（oldtime0="

newtime0<

if（oldtime1="

0101"

newtime1<

elsenewtime1<

=oldtime1+'

elsenewtime0<

=oldtime0+'

endaddsec_addmin;

proceduresubsec_submin（oldtime0,oldtime1:

begin--秒、分减

=oldtime1-'

=oldtime0-'

endsubsec_submin;

procedureaddhour（oldhour0,oldhour1:

begin--时加

if（oldhour0="

newhour0<

newhour1<

=oldhour1+'

elsenewhour0<

=oldhour0+'

andoldhour1="

newhour1<

endaddhour;

proceduresubhour（oldhour0,oldhour1:

begin--时减

=oldhour1-'

=oldhour0-'

endsubhour;

2、顶层模块

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

useIEEE.STD_LOGIC_ARITH.ALL;

useIEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncommentthefollowinglinestousethedeclarationsthatare

--providedforinstantiatingXilinxprimitivecomponents.

--libraryUNISIM;

--useUNISIM.VComponents.all;

entitytimekeeperis

port（up,setpin,upclk,f1000:

pass,stop,enable:

a0,a1,b0,b1,c0,c1,d0:

outstd_logic_vector（3downto0）;

z:

outstd_logic;

sp:

outstd_logic）;

endtimekeeper;

architectureBehavioraloftimekeeperis

componentfenpinport（f1000:

second_wave:

bufferstd_logic）;

endcomponent;

componenth_m_sport（clk0,clk1,ce:

sec0,sec1:

bufferstd_logic_vector（3downto0）;

set:

instd_logic_vector（3downto0）;

up:

min0,min1:

hour0,hour1:

z,ov:

componentdateport（clk0,clk1,ce:

instd_logic;

up:

mon0,mon1,year0,year1:

date0,date1:

ov:

componentyear_monport（clk0,clk1,ce:

std_logic_vector（3downto0）;

mon0,mon1:

year0,year1:

bufferstd_logic_vector（3downto0））;

componentledport（set:

std_logic_vector（3downto0）;

sec0,sec1,min0,min1,hour0,hour1:

a0,a1,b0,b1,c0,c1:

nm1,nm0,nh1,nh0:

date0,date1,mon0,mon1,year0,year1:

instd_logic_vector（3downto0））;

componentalarmport（clk1,ce:

bufferstd_logic_vector（3downto0）:

）;

componentwe