电子eda实验考试题目Word下载.docx
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0'
);
else
ifcnt="
00111111"
="
00000000"
;
co<
='
else
=cnt+'
endif;
endprocess;
process(clk1)
ifclk1'
eventandclk1='
scan<
=notscan;
endprocess;
ledout<
=notled;
scanout<
=scan;
hex<
=cnt(7downto4)whenscan='
elsecnt(3downto0);
withhexselect
led<
1111001"
when"
0001"
"
0100100"
0010"
0110000"
0011"
0011001"
0100"
0010010"
0101"
0000010"
0110"
1111000"
0111"
0000000"
1000"
0010000"
1001"
0001000"
1010"
0000011"
1011"
1000110"
1100"
0100001"
1101"
0000110"
1110"
0001110"
1111"
1000000"
whenothers;
enda;
2、设计一个带计数使能、异步复位、带进位输出的增1二十进制计数器,计数结果由共阴极七段数码管显示
port(clk,clk1,en,clr:
co,scanout:
outstd_logic;
outstd_logic_vector(6downto0));
architecturertlofcounteris
signalcnt:
signalled:
signalscan:
signalhex:
process(clk,clr)
elsifclk'
then
00001001"
00010000"
elsifcnt="
00011001"
then--注意此处,前面跳过了A到F的计数,所以计数到11001
process(clk1)
ledout<
scanout<
hex<
withhexselect
led<
0000"
1111111"
endrtl;
。
3、设计一个带计数使能、同步复位、同步装载的可逆七位二进制计数器,计数结果由共阴极七段数码管显示。
port(clk,clks,clr,en,stdl,dir:
din:
instd_logic_vector(6downto0);
scanout:
elsifstdl='
=din;
elsifen='
ifdir='
=cnt-'
process(clks)
if(clks'
eventandclks='
&
cnt(6downto4)whenscan='
elsecnt(3downto0);
4、设计一个带计数使能、异步复位、异步装载、可逆计数的通用计数器。
计数结果由共阴极七段数码管显示。
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYcounterIS
GENERIC(count_value:
INTEGER:
=9);
PORT(clk,clr,en,load,dir:
INSTD_LOGIC;
data_in:
ININTEGERRANGE0TOcount_value;
OUTSTD_LOGIC_VECTOR(6DOWNTO0));
ENDcounter;
ARCHITECTUREaOFcounterIS
SIGNALcnt:
INTEGERRANGE0TOcount_value;
SIGNALled:
STD_LOGIC_VECTOR(6DOWNTO0);
BEGIN
PROCESS(load,clk)
BEGIN
IFload='
THEN
=data_in;
elsifclr='
=0;
ELSIF(clk'
EVENTANDclk='
)THEN
IFen='
IFdir='
IFcnt=count_valueTHEN
ELSE
=cnt+1;
IFcnt=0THEN
=count_value;
=cnt-1;
ENDPROCESS;
=NOTled;
WITHcntSELECT
WHEN1,
WHEN2,
WHEN3,
WHEN4,
WHEN5,
WHEN6,
WHEN7,
WHEN8,
WHEN9,
WHEN0,
WHENothers;
ENDa;
5、设计一个具有16分频、8分频、4分频和2分频功能的分频器
ENTITYdiv4IS
PORT(clk:
INSTD_LOGIC_VECTOR(3DOWNTO0);
fout:
OUTstd_LOGIC);
ENDdiv4;
ARCHITECTUREaOFdiv4IS
variablecnt:
)then
cnt:
ifdin="
fout<
=cnt(3);
elsifdin="
=cnt
(2);
=cnt
(1);
=cnt(0);
6、设计一个正负脉宽相等的通用分频器
ENTITYdivIS
GENERIC(num:
=2);
PORT
(clk:
co:
OUTSTD_LOGIC);
ENDdiv;
ARCHITECTURErtlOFdivIS
PROCESS(clk)
VARIABLEcnt:
STD_LOGIC_VECTOR(numdownto0);
IF(clk'
ENDIF;
=cnt(num);
ENDrtl;
7、设计一个正负脉宽可控的16分频的分频器
COUNT:
SIGNALco:
STD_LOGIC;
count<
=co;
STD_LOGIC_VECTOR(3DOWNTO0);
if(cnt="
=notco;
elsif(cnt=din)then
8、根据需要设计一个分频器:
可以控制实现四种分频形式:
第一种:
8分频、第二种:
10分频、第三种:
15分频、第四种:
16分频,其中8分频和16分频为正负脉宽相等的分频器
entityfenpinis
port(clk:
en:
instd_logic_vector(1downto0);
cout:
endfenpin;
architecturedgnfenpinoffenpinis
process(clk)
eventANDclk='
if(en="
00"
if(cnt>
cout<
elsif(en="
01"
10"
cout<
endif;
withenselect
11"
enddgnfenpin;
9、设计一个M序列发生器,M序列为“11100111”(修改序列数原为1101101)
USEIEEE.STD_logic_1164.all;
ENTITYSEQIS
PORT(
CLK:
INSTD_logic;
FOUT:
OUTSTD_logic);
ENDSEQ;
ARCHITECTUREBEHAVEOFSEQIS
SIGNALCNT:
STD_logic_VECTOR(2DOWNTO0);
PROCESS(CLK)
IFCLK'
EVENTANDCLK='
IFCNT="
111"
CNT<
000"
ELSE
=CNT+'
ENDIF;
ENDPROCESS;
WITHCNTSELECT
FOUT<
WHEN"
001"
010"
011"
100"
101"
110"
when"
WHENOTHERS;
endBEHAVE;
10、设计一个彩灯控制器,彩灯共有21个,每次顺序点亮相邻的3个彩灯,如此循环执行,循环的方向可以控制(原为16个)
entitycaidengis
port(rl,clk:
ledout:
outstd_logic_vector(15downto0));
endcaideng;
architectureaofcaidengis
std_logic_vector(15downto0);
signalk:
if(clk'
if(k='
=(0=>
1=>
2=>
others=>
k<
elsif(rl='
=led(14downto0)&
led(15);
=led(0)&
led(15downto1);
=led;
11、设计一个具有左移、右移控制,同步并行装载和串行装载的8位串行移位寄存器,每次移位为1位
ENTITYshifter1IS
PORT(clk,clr,ser,dir,stld:
din:
INSTD_LOGIC_VECTOR(0TO7);
qh:
ENDshifter1;
ARCHITECTURErt1OFshifter1IS
SIGNALreg:
STD_LOGIC_VECTOR(0TO7);
process(clk,clr)
ifclr='
reg<
elsifclk'
ifstld='
reg<
if(dir='
=reg(1to7)&
ser;
qh<
=reg(0);
=ser&
reg(0to6);
=reg(7);
endrt1;
12、设计一个15人表决电路,参加表决者为15人,同意为1,不同意为0,同意者过半则表决通过,绿指示灯亮,表决不通过则红指示灯亮。
数码管显示赞成人数。
(原来为7人)
entityselectoris
port(b:
clr:
red,gree:
endselector;
architecturertlofselectoris
std_logic_v