慢速充电时钟芯片DS1302中英文资料.docx

慢速充电时钟芯片DS1302中英文资料.docx

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慢速充电时钟芯片DS1302中英文资料

DS1302TrickleChargeTimekeepingChip

一、FEATURES

1、Realtimeclockcountsseconds,minuteshours,dateofthemonth,month,dayoftheweek,andyearwithleapyearcompensationvalidupto2100.

2、31x8RAMforscratchpaddatastorage.

3、SerialI/Oforminimumpincount.

4、2.0–5.5Vfulloperation.

5、Useslessthan300nAat2.0V.

6、Single–byteormultiple–byte（burstmode）datatransferforreadorwriteofclockorRAMdata.

7、8–pinDIPoroptional8–pinSOICsforsurfacemount.

8、Simple3–wireinterface.

9、TTL–compatible（VCC=5V）.

10、Optionalindustrialtemperaturerange–40°Cto+85°C.

11、DS1202compatible.

二、PINASSIGNMENT

三、PINDESCRIPTION

①X1,X2：

32.768kHzCrystalPins；②GND：

Ground；③RST：

Reset；④I/O：

DataInput/Output；⑤SCLK：

SerialClock；⑥VCC1,VCC2：

PowerSupplyPins

四、DESCRIPTION

TheDS1302TrickleChargeTimekeepingChipcontainsarealtimeclock/calendarand31bytesofstaticRAM.Itcommunicateswithamicroprocessorviaasimpleserialinterface.Therealtimeclock/calendarprovidesseconds,minutes,hours,day,date,month,andyearinformation.Theendofthemonthdateisautomaticallyadjustedformonthswithlessthan31days,includingcorrectionsforleapyear.Theclockoperatesineitherthe24–houror12–hourformatwithanAM/PMindicator.InterfacingtheDS1302withamicroprocessorissimplifiedbyusingsynchronousserialcommunication.Onlythreewiresarerequiredtocommunicatewiththeclock/RAM:

（1）RST（Reset）,

（2）I/O（Dataline）,and（3）SCLK（Serialclock）.Datacanbetransferredtoandfromtheclock/RAM1byteatatimeorinaburstofupto31bytes.TheDS1302isdesignedtooperateonverylowpowerandretaindataandclockinformationonlessthan1microwatt.

TheDS1302isthesuccessortotheDS1202.InadditiontothebasictimekeepingfunctionsoftheDS1202,theDS1302hastheadditionalfeaturesofdualpowerpinsforprimaryandback–uppowersupplies,programmabletricklechargerforVCC1,andsevenadditionalbytesofscratchpadmemory.

（1）、OPERATION

ThemainelementsoftheSerialTimekeeperareshowninFigure1:

shiftregister,controllogic,oscillator,realtimeclock,andRAM.

DS1302BLOCKDIAGRAMFigure1

（2）、SIGNALDESCRIPTIONS

①VCC1：

VCC1provideslowpoweroperationinsinglesupplyandbatteryoperatedsystemsaswellaslowpowerbatterybackup.Insystemsusingthetricklecharger,therechargeableenergysourceisconnectedtothispin.

②VCC2：

Vcc2istheprimarypowersupplypininadualsupplyconfiguration.VCC1isconnectedtoabackupsourcetomaintainthetimeanddateintheabsenceofprimarypower.

③TheDS1302willoperatefromthelargerofVCC1orVCC2.WhenVCC2isgreaterthanVCC1+0.2V,VCC2willpowertheDS1302.WhenVCC2islessthanVCC1,VCC1willpowertheDS1302.

④SCLK（SerialClockInput）–SCLKisusedtosynchronizedatamovementontheserialinterface.

⑤I/O（DataInput/Output）–TheI/Opinisthebi-directionaldatapinforthe3-wireinterface.

⑥RST（Reset）–Theresetsignalmustbeassertedhighduringareadorawrite.

⑦X1,X2：

Connectionsforastandard32.768kHzquartzcrystal.Theinternaloscillatorisdesignedforoperationwithacrystalhavingaspecifiedloadcapacitanceof6pF.

（3）、COMMANDBYTE

ThecommandbyteisshowninFigure2.Eachdatatransferisinitiatedbyacommandbyte.TheMSB（Bit7）mustbealogic1.Ifitis0,writestotheDS1302willbedisabled.Bit6specifiesclock/calendardataiflogic0orRAMdataiflogic1.Bits1through5specifythedesignatedregisterstobeinputoroutput,andtheLSB（bit0）specifiesawriteoperation（input）iflogic0orreadoperation（output）iflogic1.ThecommandbyteisalwaysinputstartingwiththeLSB（bit0）.

ADDRESS/COMMANDBYTEFigure2

（4）、RESETANDCLOCKCONTROL

AlldatatransfersareinitiatedbydrivingtheRSTinputhigh.TheRSTinputservestwofunctions.First,RSTturnsonthecontrollogicwhichallowsaccesstotheshiftregisterfortheaddress/commandsequence.Second,theRSTsignalprovidesamethodofterminatingeithersinglebyteormultiplebytedatatransfer.Aclockcycleisasequenceofafallingedgefollowedbyarisingedge.Fordatainputs,datamustbevalidduringtherisingedgeoftheclockanddatabitsareoutputonthefallingedgeofclock.IftheRSTinputislowalldatatransferterminatesandtheI/Opingoestoahighimpedancestate.DatatransferisillustratedinFigure3.Atpower–up,RSTmustbealogic0untilVCC>2.0volts.AlsoSCLKmustbeatalogic0whenRSTisdriventoalogic1state.

DATATRANSFERSUMMARYFigure3

（5）、DATAINPUT

FollowingtheeightSCLKcyclesthatinputawritecommandbyte,adatabyteisinputontherisingedgeofthenexteightSCLKcycles.AdditionalSCLKcyclesareignoredshouldtheyinadvertentlyoccur.Dataisinputstartingwithbit0.

（6）、DATAOUTPUT

FollowingtheeightSCLKcyclesthatinputareadcommandbyte,adatabyteisoutputonthefallingedgeofthenexteightSCLKcycles.Notethatthefirstdatabittobetransmittedoccursonthefirstfallingedgeafterthelastbitofthecommandbyteiswritten.AdditionalSCLKcyclesretransmitthedatabytesshouldtheyinadvertentlyoccursolongasRSTremainshigh.Thisoperationpermitscontinuousburstmodereadcapability.Also,theI/Opinistri–stateduponeachrisingedgeofSCLK.Dataisoutputstartingwithbit0.

（7）、BURSTMODE

Burstmodemaybespecifiedforeithertheclock/calendarortheRAMregistersbyaddressinglocation31decimal（address/commandbits1through5=logic1）.Asbefore,bit6specifiesclockorRAMandbit0specifiesreadorwrite.Thereisnodatastoragecapacityatlocations9through31intheClock/CalendarRegistersorlocation31intheRAMregisters.Readsorwritesinburstmodestartwithbit0ofaddress0.Whenwritingtotheclockregistersintheburstmode,thefirsteightregistersmustbewritteninorderforthedatatobetransferred.However,whenwritingtoRAMinburstmodeitisnotnecessarytowriteall31bytesforthedatatotransfer.EachbytethatiswrittentowillbetransferredtoRAMregardlessofwhetherall31bytesarewrittenornot.

（8）、CLOCK/CALENDAR

Theclock/calendariscontainedinsevenwrite/readregistersasshowninFigure4.Datacontainedintheclock/calendarregistersisinbinarycodeddecimalformat（BCD）.

REGISTERADDRESS/DEFINITIONFigure4：

（9）、CLOCKHALTFLAG

Bit7ofthesecondsregisterisdefinedastheclockhaltflag.Whenthisbitissettologic1,theclockoscillatorisstoppedandtheDS1302isplacedintoalow–powerstandbymodewithacurrentdrainoflessthan100nanoamps.Whenthisbitiswrittentologic0,theclockwillstart.Theinitialpoweronstateisnotdefined.

（10）、AM-PM/12-24MODE

Bit7ofthehoursregisterisdefinedasthe12–or24–hourmodeselectbit.Whenhigh,the12–hourmodeisselected.Inthe12–hourmode,bit5istheAM/PMbitwithlogichighbeingPM.Inthe24–hourmode,bit5isthesecond10-hourbit（20–23hours）.

（11）、WRITEPROTECTBIT

Bit7ofthecontrolregisteristhewrite-protectbit.Thefirstsevenbits（bits0–6）areforcedto0andwillalwaysreada0whenread.BeforeanywriteoperationtotheclockorRAM,bit7mustbe0.Whenhigh,thewriteprotectbitpreventsawriteoperationtoanyotherregister.Theinitialpoweronstateisnotdefined.ThereforetheWPbitshouldbeclearedbeforeattemptingtowritetothedevice.

（12）、TRICKLECHARGEREGISTER

ThisregistercontrolsthetricklechargecharacteristicsoftheDS1302.ThesimplifiedschematicofFigure5showsthebasiccomponentsofthetricklecharger.Thetricklechargeselect（TCS）bits（bits4-7）controltheselectionofthetricklecharger.Inordertopreventaccidentalenabling,onlyapatternof1010willenablethetricklecharger.Allotherpatternswilldisablethetricklecharger.TheDS1302powersupwiththetricklechargerdisabled.Thediodeselect（DS）bits（bits2–3）selectwhetheronediodeortwodiodesareconnectedbetweenVCC2andVCC1.IfDSis01,onediodeisselectedorifDSis10,twodiodesareselected.IfDSis00or11,thetricklechargerisdisabledindependentlyofTCS.TheRSbits（bits0-1）selecttheresistorthatisconnectedbetweenVCC2andVCC1.Theresistorselectedbytheresistorselect（RS）bitsisasfollows.

IfRSis00,thetricklechargerisdisabledindependentlyofTCS.

Diodeandresistorselectionisdeterminedbytheuseraccordingtothemaximumcurrentdesiredforbatteryorsupercapcharging.Themaximumchargingcurrentcanbecalculatedasillustratedinthefollowingexample.Assumethatasystempowersupplyof5voltisappliedtoVCC2andasupercapisconnectedtoVCC1.AlsoassumethatthetricklechargerhasbeenenabledwithonediodeandresistorR1betweenVCC2andVCC1.ThemaximumcurrentImaxwouldthereforebecalculatedasfollows:

Imax=（5.0V–diodedrop）/R1

~（5.0V–0.7V）/2kΩ

~2.2Ma

Obviously,asthesupercapcharges,thevoltagedropbetweenVCC2andVCC1willdecreaseandthereforethechargecurrentwilldecrease.

（13）、CLOCK/CALENDARBURSTMODE

Theclock/calendarcommandbytespecifiesburstmodeoperation.Inthismodethefirsteightclock/calendarregisterscanbeconsecutivelyreadorwritten（seeFigure4）startingwithbit0ofaddress0.Ifthewriteprotectbitissethighwhenawriteclock/calendarburstmodeisspecified,nodatatransferwilloccurtoanyoftheeightclock/calendarregisters（thisincludesthecontrolregister）.Thetricklechargerisnotaccessibleinburstmode.Atthebeginningofaclockburstread,thecurrenttimeistransferredtoasecondsetofregisters.Thetimeinformationisreadfromthesesecondaryregisters,whiletheclockmaycont