EDA课设实验报告数字时钟.docx
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EDA课设实验报告数字时钟
EDA课设
设计要求
1具有时，分秒，计数显示功能，以24小时循环计时。
2具有清零，调节小时，分钟功能。
3具有整点报时功能。
实验目的
1掌握多位计数器相连的设计方法。
2掌握十进制，六进制。
二十四进制计数器的设计方法。
3巩固多位共阴极扫描显示数码管的驱动及编码。
4掌握扬声器的驱动。
5掌握EDA技术的层次化设计方法。
顶层文件数字时钟各模块连接图
程序
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYSZZIS
PORT（CLK,RESET,SETMIN,SETHOUR,CLKDSP:
INSTD_LOGIC;
SPEAKER:
OUTSTD_LOGIC;
LAMP:
OUTSTD_LOGIC_VECTOR（2DOWNTO0）;
SEL:
OUTSTD_LOGIC_VECTOR（2DOWNTO0）;
A,B,C,D,E,F,G,DPOUT:
OUTSTD_LOGIC）;
ENDSZZ;
ARCHITECTUREONEOFSZZIS
COMPONENTSECOND
PORT（CLK,RESET,SETMIN:
INSTD_LOGIC;
DAOUT:
OUTSTD_LOGIC_VECTOR（6DOWNTO0）;
ENMIN:
OUTSTD_LOGIC）;
ENDCOMPONENT;
COMPONENTMINUTE
PORT（CLK,CLK1,RESET,SETHOUR:
INSTD_LOGIC;
ENHOUR:
OUTSTD_LOGIC;
DAOUT:
OUTSTD_LOGIC_VECTOR（6DOWNTO0））;
ENDCOMPONENT;
COMPONENTHOUR
PORT（CLK,RESET:
INSTD_LOGIC;
DAOUT:
OUTSTD_LOGIC_VECTOR（5DOWNTO0））;
ENDCOMPONENT;
COMPONENTALERT
PORT（CLK:
INSTD_LOGIC;
DAIN:
INSTD_LOGIC_VECTOR（6DOWNTO0）;
LAMP:
OUTSTD_LOGIC_VECTOR（2DOWNTO0）;
SPEAK:
OUTSTD_LOGIC）;
ENDCOMPONENT;
COMPONENTSELTIME
PORT（CLK1,RESET:
INSTD_LOGIC;
SEC,MIN:
INSTD_LOGIC_VECTOR（6DOWNTO0）;
HOUR:
INSTD_LOGIC_VECTOR（5DOWNTO0）;
DP:
OUTSTD_LOGIC;
DAOUT:
OUTSTD_LOGIC_VECTOR（3DOWNTO0）;
SEL:
OUTSTD_LOGIC_VECTOR（2DOWNTO0））;
ENDCOMPONENT;
COMPONENTDELED
PORT（
NUM:
INSTD_LOGIC_VECTOR（3DOWNTO0）;
LED:
OUTSTD_LOGIC_VECTOR（6DOWNTO0））;
ENDCOMPONENT;
SIGNALENMIN_RE,ENHOUR_RE:
STD_LOGIC;
SIGNALSECOND_DAOUT,MINUTE_DAOUT:
STD_LOGIC_VECTOR（6DOWNTO0）;
SIGNALHOUR_DAOUT:
STD_LOGIC_VECTOR（5DOWNTO0）;
SIGNALSELTIME_DAOUT:
STD_LOGIC_VECTOR（3DOWNTO0）;
SIGNALLEDOUT:
STD_LOGIC_VECTOR（6DOWNTO0）;
BEGIN
A<=LEDOUT（6）;B<=LEDOUT（5）;C<=LEDOUT（4）;D<=LEDOUT（3）;
E<=LEDOUT
（2）;F<=LEDOUT
（1）;G<=LEDOUT（0）;
U1:
SECONDPORTMAP（RESET=>RESET,
CLK=>CLK,
SETMIN=>SETMIN,
ENMIN=>ENMIN_RE,
DAOUT=>SECOND_DAOUT）;
U2:
MINUTEPORTMAP（CLK=>ENMIN_RE,
CLK1=>CLK,
RESET=>RESET,
SETHOUR=>SETHOUR,
ENHOUR=>ENHOUR_RE,
DAOUT=>MINUTE_DAOUT）;
U3:
HOURPORTMAP（CLK=>ENHOUR_RE,
RESET=>RESET,
DAOUT=>HOUR_DAOUT）;
U4:
ALERTPORTMAP（CLK=>CLK,
DAIN=>MINUTE_DAOUT,
SPEAK=>SPEAKER,
LAMP=>LAMP）;
U5:
SELTIMEPORTMAP（CLK1=>CLKDSP,
RESET=>RESET,
SEC=>SECOND_DAOUT,
MIN=>MINUTE_DAOUT,
HOUR=>HOUR_DAOUT,
DAOUT=>SELTIME_DAOUT,
DP=>DPOUT,
SEL=>SEL）;
U6:
DELEDPORTMAP（NUM=>SELTIME_DAOUT,
LED=>LEDOUT）;
ENDONE;
仿真图
2秒计数器
程序
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitysecondis
port（
clk,reset,setmin:
instd_logic;
enmin:
outstd_logic;
daout:
outstd_logic_vector（6downto0））;
endentitysecond;
architecturefunofsecondis
signalcount:
std_logic_vector（6downto0）;
signalenmin_1,enmin_2:
std_logic;
begin
daout<=count;
enmin_2<=（setminandclk）;
enmin<=（enmin_1orenmin_2）;
process（clk,reset,setmin）
begin
if（reset='0'）thencount<="0000000";
elsif（clk'eventandclk='1'）then
if（count（3downto0）="1001"）then
if（count<16#60#）then
if（count="1011001"）then
enmin_1<='1';count<="0000000";
else
count<=count+7;
endif;
else
count<="0000000";
endif;
elsif（count<16#60#）then
count<=count+1;
enmin_1<='0'after100ns;
else
count<="0000000";
endif;
endif;
endprocess;
endfun;
仿真图
3.分计时器
程序
LIBRARYieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
ENTITYminuteIS
PORT（
clk,clk1,reset,sethour:
INSTD_LOGIC;
enhour:
OUTSTD_LOGIC;
daout:
outstd_logic_vector（6downto0））;
ENDENTITYminute;
ARCHITECTUREfunOFminuteIs
SIGNALcount:
STD_LOGIC_VECTOR（6downto0）;
SIGNALenhour_1,enhour_2:
STD_LOGIC;
BEGIN
daout<=count;
enhour_2<=（sethourandclk1）;
enhour<=（enhour_1orenhour_2）;
process（clk,reset,sethour）
begin
if（reset='0'）then
count<="0000000";
elsif（clk'eventandclk='1'）then
if（count（3downto0）="1001"）then
if（count<16#60#）then
if（count="1011001"）then
enhour_1<='1';
count<="0000000";
ELSE
count<=count+7;
endif;
else
count<="0000000";
endif;
elsif（count<16#60#）then
count<=count+1;
enhour_1<='0'after100ns;
else
count<="0000000";
endif;
endif;
endprocess;
ENDfun;
仿真图
4小时文本
程序
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityhouris
port（
clk,reset:
instd_logic;
daout:
outstd_logic_vector（5downto0））;
endhour;
architecturefunofhouris
signalcount:
std_logic_vector（5downto0）;
begin
daout<=count;
process（clk,reset）
begin
if（reset='0'）then
count<="000000";
elsif（clk'eventandclk='1'）then
if（count（3downto0）="1001"）then
if（count<16#23#）then
count<=count+7;
else
count<="000000";
endif;
elsif（count<16#23#）then
count<=count+1;
else
count<="000000";
endif;
endif;
endprocess;
endfun;
仿真图
5报警文本
程序
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYALERTIS
PORT（
CLK:
INSTD_LOGIC;
DAIN:
INSTD_LOGIC_VECTOR（6DOWNTO0）;
SPEAK:
OUTSTD_LOGIC;
LAMP:
OUTSTD_LOGIC_VECTOR（2DOWNTO0））;
ENDALERT;
ARCHITECTUREFIVEOFALERTIS
SIGNALCOUNT:
STD_LOGIC_VECTOR（1DOWNTO0）;
SIGNALCOUNT1:
STD_LOGIC_VECTOR（1DOWNTO0）;
BEGIN
SPEAKER:
PROCESS（CLK）
BEGIN
SPEAK<=COUNT1
（1）;
IF（CLK'EVENTANDCLK='1'）THEN
IF（DAIN="0000000"）THEN
IF（COUNT1>="10"）THEN
COUNT1<="00";
ELSE
COUNT1<=COUNT1+1;
ENDIF;
ENDIF;
ENDIF;
ENDPROCESSSPEAKER;
LAMPER:
PROCESS（CLK）
BEGIN
IF（RISING_EDGE（CLK））THEN
IF（COUNT<="10"）THEN
IF（COUNT<="00"）THEN
LAMP<="001";
ELSIF（COUNT<="01"）THEN
LAMP<="010";
ELSIF（COUNT<="10"）THEN
LAMP<="100";
ENDIF;
COUNT<=COUNT+1;
ELSE
COUNT<="00";
ENDIF;
ENDIF;
ENDPROCESSLAMPER;
ENDFIVE;
仿真图
6时间数据扫描分时选择模块文本
程序
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYSELTIMEIS
PORT（
CLK1,RESET:
INSTD_LOGIC;
SEC,MIN:
INSTD_LOGIC_VECTOR（6DOWNTO0）;
HOUR:
INSTD_LOGIC_VECTOR（5DOWNTO0）;
DAOUT:
OUTSTD_LOGIC_VECTOR（3DOWNTO0）;
DP:
OUTSTD_LOGIC;
SEL:
OUTSTD_LOGIC_VECTOR（2DOWNTO0））;
ENDSELTIME;
ARCHITECTURESIXOFSELTIMEIS
SIGNALCOUNT:
STD_LOGIC_VECTOR（2DOWNTO0）;
BEGIN
SEL<=COUNT;
PROCESS（CLK1,RESET）
BEGIN
IF（RESET='0'）THEN
COUNT<="000";
ELSIF（CLK1'EVENTANDCLK1='1'）THEN
IF（COUNT>="101"）THEN
COUNT<="000";
ELSE
COUNT<=COUNT+1;
ENDIF;
ENDIF;
CASECOUNTIS
WHEN"000"=>DAOUT<=SEC（3DOWNTO0）;DP<='0';
WHEN"001"=>DAOUT（3）<='0';
DAOUT（2DOWNTO0）<=SEC（6DOWNTO4）;
DP<='0';
WHEN"010"=>DAOUT<=MIN（3DOWNTO0）;DP<='1';
WHEN"011"=>DAOUT（3）<='0';
DAOUT（2DOWNTO0）<=MIN（6DOWNTO4）;
DP<='0';
WHEN"100"=>DAOUT<=HOUR（3DOWNTO0）;DP<='1';
WHENOTHERS=>DAOUT（3DOWNTO2）<="00";
DAOUT（1DOWNTO0）<=HOUR（5DOWNTO4）;
DP<='0';
ENDCASE;
ENDPROCESS;
ENDSIX;
仿真图
7译码器文本
程序
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYDELEDIS
PORT（NUM:
INSTD_LOGIC_VECTOR（3DOWNTO0）;
LED:
OUTSTD_LOGIC_VECTOR（6DOWNTO0））;
ENDDELED;
ARCHITECTURESEVENOFDELEDIS
BEGIN
LED<="1111110"WHENNUM="0000"ELSE
"0110000"WHENNUM="0001"ELSE
"1101101"WHENNUM="0010"ELSE
"1111001"WHENNUM="0011"ELSE
"0110011"WHENNUM="0100"ELSE
"1011011"WHENNUM="0101"ELSE
"1011111"WHENNUM="0110"ELSE
"1110000"WHENNUM="0111"ELSE
"1111111"WHENNUM="1000"ELSE
"1111011"WHENNUM="1001"ELSE
"1110111"WHENNUM="1010"ELSE
"0011111"WHENNUM="1011"ELSE
"1001110"WHENNUM="1100"ELSE
"0111101"WHENNUM="1101"ELSE
"1001111"WHENNUM="1110"ELSE
"1000111"WHENNUM="1111";
ENDSEVEN;
仿真图
设计中遇到的问题与体会
在置数方面第一次写时在时钟沿内同步置数下载在试验箱上很难实现于是把置数改成异步置数。
在报时模块一直没搞清需要达到怎样的报时效果所以花费时间最长。
在设计数字时钟时通过解决在编程调试以及仿真过程中出现的种种问题加深了我们对软件设计坏境的熟悉程度。
令我印象最深的就是在编程中虽然有些程序的结构获得的效果以及软件仿真的结果是一致的但在实际硬件实现却会有很大的不同。
通过设计我们更深的认识了EDA技术受益匪浅。
升级会员 