AT89C51外文翻译毕业设计.docx

AT89C51外文翻译毕业设计.docx

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AT89C51外文翻译毕业设计

AT89C51外文翻译毕业设计

AT89C51

外文翻译

Description

TheAT89C51isalow-powerhigh-performanceCMOS8-bitmicrocomputerwith4KbytesofFlashProgrammableandErasableReadOnlyMemoryPEROM

ThedeviceismanufacturedusingAtmelshighdensitynonvolatilememorytechnologyandiscompatiblewiththeindustrystandardMCS-51instruction-setandpinoutTheon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememoryprogrammerBycombiningaversatile8-bitCPUwithFlashonamonolithicchiptheAtmelAT89C51isapowerfulmicrocomputerwhichprovidesahighlyflexibleandcosteffectivesolutiontomanyembeddedcontrolapplications

Features

CompatiblewithMCS-51Products

4KBytesofIn-SystemReprogrammableFlashMemory

-Enduranee1000WriteEraseCycles

FullyStaticOperation0Hzto24MHz

Three-LevelProgramMemoryLock

128x8-BitInternalRAM

32ProgrammableIOLines

Two16-BitTimerCounters

SixInterruptSources

ProgrammableSerialChannel

LowPowerIdleandPowerDownModes

TheAT89C51providesthefollowingstandardfeatures4Kbytesof

Flash128bytesofRAM32IOlinestwo16-bittimercountersafivevectoroscillatorandclockcircuitryInadditiontheAT89C51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodesTheIdleModestopstheCPUwhile

allowingtheRAMtimercountersserialportandinterruptsystemtocontinuefunctioningThePower-downModesavestheRAMcontentsbutfreezestheoscillatordisablingallotherchipfunctionsuntilthenexthardwarereset

VCC

Supplyvoltage

GND

Ground

Port0

Port0isan8-bitopen-drainbi-directionalIOportAsanoutputporteachpincansinkeightTTLinputsWhen1sarewrittentoport0pinsthe

pinscanbeusedashigh-impedanceinputs

Port0mayalsobeconfiguredtobethemultiplexedlow-orderaddressdatabusduringaccessestoexternalprogramanddatamemoryInthismodeP0hasinternalpullups

Port0alsoreceivesthecodebytesduringFlashprogrammingandoutputsthecodebytesduringprogramverificationExternalpullupsarerequiredduringprogramverification

Port1

Port1isan8-bitbi-directionalIOportwithinternalpullupsThe

Port1outputbufferscansinksourcefourTTLinputsWhen1sarewritten

low

toPort1pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputsAsinputsPort1pinsthatareexternallybeingpulledwillsourcecurrentIILbecauseoftheinternalpullupsPort1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification

Port2

Port2isan8-bitbi-directionalIOportwithinternalpullupsThe

Port2outputbufferscansinksourcefourTTLinputsWhen1sarewrittentoPort2pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputsAsinputsPort2pinsthatareexternallybeingpulledlowwillsourcecurrentIILbecauseoftheinternalpullups

Port2emitsthehigh-orderaddressbyteduringfetchesfromexternal

programmemoryandduringaccessestoexternaldatamemorythatuse16-bitaddressesMOVXDPTRInthisapplicationitusesstronginternalpullupswhenemitting1sDuringaccessestoexternaldatamemorythatuse8-bitaddressesMOVXRIPort2emitsthecontentsoftheP2SpecialFunction

RegisterPort2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification

Port3

Port3isan8-bitbi-directionalIOportwithinternalpullupsThe

Port3outputbufferscansinksourcefourTTLinputsWhen1sarewritten

low

toPort3pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputsAsinputsPort3pinsthatareexternallybeingpulledwillsourcecurrentIILbecauseofthepullupsPort3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89C51aslistedbelow

Port3alsoreceivessomecontrolsignalsforFlashprogrammingandverification

RST

ResetinputAhighonthispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedevice

ALEPROG

AddressLatchEnableoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemoryThispinisalsotheprogrampulseinputPROGduringFlashprogrammingInnormaloperationALEisemittedataconstantrateof16theoscillatorfrequencyandmaybeusedforexternaltimingorclockingpurposesNotehoweverthatoneALEpulseisskippedduringeachaccesstoexternalData

Memory

IfdesiredALEoperationcanbedisabledbysettingbit0ofSFRlocation8EHWiththebitsetALEisactiveonlyduringaMOVXorMOVCinstructionOtherwisethepinisweaklypulledhighSettingthe

ALE-disablebithasnoeffectifthemicrocontrollerisinexternalexecutionmode

PSEN

ProgramStoreEnableisthereadstrobetoexternalprogrammemory

WhentheAT89C51isexecutingcodefromexternalprogrammemoryPSENisactivatedtwiceeachmachinecycleexceptthattwoPSENactivationsareskippedduringeachaccesstoexternaldatamemory

EAVPP

ExternalAccessEnableEAmustbestrappedtoGNDinordertoenablethedevicetofetchcodefromexternalprogrammemorylocationsstartingat0000HuptoFFFFHNotehoweverthatiflockbit1isprogrammedEAwillbeinternallylatchedonresetEAshouldbestrappedtoVCCforinternal

the12-voltprogrammingenable

programexecutionsThispinalsoreceivesvoltageVPPduringFlashprogrammingforpartsthatrequire12-voltVPP

XTAL1

clockoperatingcircuit

XTAL2

Characteristics

amplifierwhichcanbeconfiguredforuseasanon-chiposcillatorasshowninFigure1EitheraquartzcrystalorceramicresonatormaybeusedTodrivethedevicefromanexternalclocksourceXTAL2shouldbeleftunconnectedwhileXTAL1isdrivenasshowninFigure2Therearenorequirementsonthedutycycleoftheexternalclocksignalsincetheinputtotheinternalclockingcircuitryisthroughadivide-by-twoflip-flopbutminimumandimumvoltagehighandlowtimespecificationsmustbeobserved

IdleMode

InidlemodetheCPUputsitselftosleepwhilealltheon-chipperipheralsremainactiveThemodeisinvokedbysoftwareThecontentoftheon-chipRAMandallthespecialfunctionsregistersremainunchangedduringthismodeTheidlemodecanbeterminatedbyanyenabledinterruptorbyahardwareresetItshouldbenotedthatwhenidleisterminatedbyahardwareresetthedevicenormallyresumesprogramexecutionfromwhereitleftoffuptotwomachinecyclesbeforetheinternalresetalgorithmtakescontrolOn-chiphardwareinhibitsaccesstointernalRAMinthiseventbutaccesstotheportpinsisnotinhibitedToeliminatethepossibilityofanunexpectedwritetoaportpinwhenIdleisterminatedbyresettheinstructionfollowingtheonethatinvokesIdleshouldnotbeonethatwritestoaportpinortoexternalmemory

Figure1OscillatorConnections

NoteC1C230pF±10pFforCrystals40pF±10pFforCeramic

Resonators

Figure2ExternalClockDriveConfiguration

Power-downMode

Inthepower-downmodetheoscillatorisstoppedandtheinstructionthatinvokespower-downisthelastinstructionexecutedTheon-chipRAMandSpecialFunctionRegistersretaintheirvaluesuntilthepower-downmodeisterminatedTheonlyexitfrompower-downisahardwareresetResetredefinestheSFRsbutdoesnotchangetheon-chipRAMTheresetshouldnotbeactivatedbeforeVCCisrestoredtoitsnormaloperatinglevelandmustbeheldactivelongenoughtoallowtheoscillatortorestartandstabilize

ProgramMemoryLockBits

OnthechiparethreelockbitswhichcanbeleftunprogrammedUorcanbeprogrammedPtoobtaintheadditionalfeatureslistedinthetablebelowWhenlockbit1isprogrammedthelogiclevelattheEApinissampledandlatchedduringresetIfthedeviceispoweredupwithoutaresetthelatchinitializestoarandomvalueandholdsthatvalueuntilresetisactivatedItisnecessarythatthelatchedvalueofEAbeinagreementwiththecurrentlogiclevelatthatpininorderforthedevicetofunctionproperly

ProgrammingtheFlash

TheAT89C51isnormallyshippedwiththeon-chipFlashmemoryarrayintheerasedstatethatiscontentsFFHandreadytobeprogrammed

Theprogramminginterfaceacceptseitherahigh-voltage12-voltoralow-voltageVCCprogramenablesignalThelow-voltageprogrammingmodeprovidesaconvenientwaytoprogramtheAT89C51insidetheuserssystemwhilethehigh-voltageprogrammingmodeiscompatiblewithconventionalthirdpartyFlashorEPROMprogrammersTheAT89C51isshippedwitheitherthehigh-voltageorlow-voltageprogrammingmodeenabledTherespectivetop-sidemarkinganddevicesignaturecodesarelistedinthefollowingtable

TheAT89C51codememoryarrayisprogrammedbyte-by-byteineitherprogrammingmodeToprogramanynon-blankbyteintheon-chipFlashMemorytheentirememorymustbeerasedusingtheChipEraseModeProgramming

AlgorithmBeforeprogrammingtheAT89C51theaddressdataandcontrolsignalsshouldbesetupaccordingtotheFlashprogrammingmodetableandFigures3and4ToprogramtheAT89C51takethefollowingsteps

1Inputthedesiredmemorylocationontheaddresslines

2Inputtheappropriatedatabyteonthedatalines

3Activatethecorrectcombinationofcontrolsignals

4RaiseEAVPPto12Vforthehigh-voltageprogrammingmode

5PulseALEPROGoncetoprogramabyteintheFlasharrayorthelockbitsThebyte-writecycleisself-timedandtypicallytakesnomorethan15msRepeatsteps1through5changingtheaddressanddatafortheentirearrayoruntiltheendoftheobjectfileisreached

DataPollingTheAT89C51featuresDataPollingtoindicatetheendofawritecycleDuringawritecyclean

attemptedreadofthelastbytewrittenwillresultinthecomplementofthewrittendatumonPO7Oncethewrite