基于单片机的指纹识别英文资料和中文翻译.docx

基于单片机的指纹识别英文资料和中文翻译.docx

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基于单片机的指纹识别英文资料和中文翻译

英文资料及中文翻译

AhybridASICandFPGAArchitecture

FPGAisEnglishFieldProgrammableGateArrayabbreviation,namelythesceneprogrammablegatearray,itistheproductwhichinPAL,GAL,EPLDandsoonintheprogrammablecomponentfoundationfurtherdevelops.Itistookinthespecial-purposeintegratedcircuit（ASIC）domainonekindpartlyhascustom-made,bothsolveshashadcustom-madetheelectriccircuitwhichtheelectriccircuitappearstheinsufficiency,andhasovercometheoriginalprogrammablecomponentgatenumberlimitedshortcoming.

FPGAusedlogicalunitarrayLCA（LogicCellArray）thiskindofnewconcept,theinteriorincludinghasbeenpossibletodisposelogicalmoduleCLB（ConfigurableLogicBlock）,outputloadmoduleIOB（InputOutputBlock）andinternalsegment（Interconnect）threeparts.TheFPGAessentialfeaturemainlyhas:

1）UsesFPGAtodesigntheASICelectriccircuit,theuserdoesnot

needtothrowthepieceproduction,canobtainthechipwhichcomesinhandy.--2）FPGAmaymakeotheralltohavecustom-madeorpartlytohavecustom-madetheASICelectriccircuittheexperimentalpreview.

2）TheFPGAinteriorhastherichtriggerandtheI/Opin.

3）FPGAisintheASICelectriccircuitdesignsthecycletobeshortest,thedevelopmentcostislowest,oneofrisksmallestcomponents.

4）FPGAisintheASICelectriccircuitdesignsthecycletobeshortest,thedevelopmentcostislowest,oneofrisksmallestcomponents.

5）FPGAusesthehighspeedCHMOScraft,thepowerlossislow,may

andCMOS,theTTLleveliscompatible.

Itcanbesaidthat,theFPGAchipisthesmallbatchsystemenhancesthesystemintegrationrate,oneofreliablebestchoices.FPGAisbydepositstheprocedureestablishesitsactivestatusininternalRAM,therefore,timeworkneedstocarryontheprogrammingtointernalRAM.Theusermayactaccordingtothedifferentdispositionpattern,selectsthedifferentprogrammingmethod.

Whenaddstheelectricity,theFPGAchipthedataread-ininternalprogramsEPROMinRAM,afterthedispositioncompletes,FPGAthrustbuild-up.Afterfallstheelectricity,FPGArestorestheunsolderedglass,internallogicrelationsvanishing,therefore,FPGAcanuserepeatedly.TheFPGAprogrammingdoesnotneedthespecial-purposeFPGAprogrammer,onlymustusegeneralEPROM,thePROMprogrammerthen.WhenneedstorevisetheFPGAfunction,onlymusttradepieceofEPROMthen.Thus,identicalpieceFPGA,thedifferentprogrammingdata,mayhavethedifferentelectriccircuitfunction.ThereforetheFPGAuseisextremelyflexible.FPGAhasmanykindsofdispositionpattern:

Parallelprincipal-mode-likeispieceofFPGAaddspieceofEPROMtheway;ThehostmaysupportpieceofPROMfromthepatterntoprogrammulti-pieceFPGA;TheserialpatternmayuseserialPROMtoprogramFPGA;TheperipheralpatternmayFPGAtakethemicroprocessortheperipheral,programsbythemicroprocessortoit.

Intheelectricalobservationandcontrolsystem,needstogathereachkindofsimulationquantitysignal,thedigitalquantitysignalfrequently,andcarriesoncorrespondingprocessingtothem.Intheordinarycircumstances,intheobservationandcontrolsystemwithordinaryMCU（forexample51,196

andsoonmonolithicintegratedcircuitsorcontrolDSP）ismaycompletethe

systemtask.。

Butwheninthesystemmustgatherthesignalquantityarespeciallymanywhen（isspeciallyeachkindofsignalquantity,conditionquantity）,dependsonmerelywiththeordinaryMCUresourcesonoftenwithdifficultycompletesthetask。

Thistime,generallyonlycanadoptthemulti-MCUin-lineprocessingpattern,ordependsonotherchipexpansionsystemresourcestocompletethesystemthemonitorduty.Notonlydidthisincreasedthemassiveexteriorelectriccircuitsandthesystemcost,moreoverincreasedthesystemcomplexitygreatly,thusthesystemreliabilitycouldreceivecertaininfluence,thiswasnotobviouslythedesigneriswillingtosee.OnekindbasedontheFPGAtechnologysimulationquantity,digitalquantitygatheringandtheprocessingsystem,usesFPGAtheI/Oporttobemany,alsomayprogramthecontrolfreely,defineitsfunctionthecharacteristic,matchesbyVHDLthecompilationFPGAinteriorexecutionsoftware,cansolvegatheringsignalwaymanyproblemswell。

BecausecompileswithVHDLtheexecutionsoftwareinteriortoeachgroupofdigitalquantityisaccordingtotheparallelprocessing,moreovertheFPGAhardwarespeedisthenslevel,thisisaspeedwhichcurrentanyMCUallwithdifficultyachieved,thereforethissystemcomparedtoothersystemscanreal-time,monitorthesignalquantityfastthechange。

Thereforeintheconditionquantityspeciallymanymonitorsystem,thissystemwillbeabletodisplayownsuperiority.

Thepracticeprovedthat,DesignstheDDSelectriccircuitwithFPGAtousethespecial-purposeDDSchiptobemorenimble.Because,solongaschangesinFPGAtheROMdata,DDSmayhavetherandomprofile,thushasthequitebigflexibility。

Comparatively:

TheFPGAfunctionisdecidedcompletelybythedesigndemand,maycomplexalsobepossibletobesimple,moreovertheFPGAchipalsosupportsinthesystemscenepromotes,althoughhastheinsufficiencyslightlyintheprecisionandthespeed,butalsocansatisfytheoverwhelmingmajoritysystembasicallytheoperationrequirements.Moreover,insertstheDDSdesigninthesystemwhichconstitutestotheFPGAchip,itssystemcostcannotincreasehowmany,butpurchasesthespecial-purposechipthepriceistheformerverymanytimes.ThereforeusesFPGAtodesigntheDDSsystemtohavetheveryhighperformance-to-priceratio.

1ApplicationsEmergeforHybridDevices

ImplementationusinganASICapproachtypicallyyieldsafaster,smaller,andlowerpowerdesignthanimplementationinFPGAtechnology.Thegrowingrequirementsinthemarketplacefordesignflexibilityhowever,aredrivingtheneedforhybridASIC/FPGAdevices.Thepotentialtochangehardwareconfigurationinrealtime,tosupportmultipledesignoptionswithasinglemaskset,andtoprolongaproduct'susablelife,allcompeldesignerstolookforablendingofhighdensityASICcircuitsalongwiththeinherentFPGAcircuitflexibility.

Theabilitytocreatea“basedesign”andthenreusethebasewithminimalchangesforsubsequentdeviceshelpsreducedesigntimeandencouragesstandardization.Sincemanyconsumerandofficeproductsareofferedwitharangeoflowtohigh-endoptions,thisbasedesignconceptcanbeeffectivelyused---withfeaturesaddedtoeachsuccessivemodel.Printers,faxmachines,PC'sanddigitalimagingequipmentareexamplewherethisconceptcanbeuseful

DSPapplicationsarealsowellsuitedtoFPGAfastmultiplyandaccumulate（MAC）processingcapability.WhenbuildingaDSPsystem,thedesigncantakeadvantageofparallelstructuresandarithmeticalgorithmstominimizeresourcesandexceedperformanceofsingleormultiplepurposeDSPdevices.DSPdesignersusingbothASICandFOGAwithinthesamedesigncanoptimizeasystemforperformancebeyondthecapabilitiesofeitherseparatecircuittechnology.

OtherapplicationsthatlendthemselvestothehybridASIC/FPGAapproacharedesignsthatsupportmultiplestandardssuchasUSB,FireWireandCameraLINK,inasingledevice.Similarly,designsthatarefinalized,withtheexceptionofanyundefinedfeaturesoremergingstandard,areexcellentcandidatesforthistechnology.Withoutthebenefitofprogrammablelogic,thedesignermustdecidebetweentaping-outthechipknowingthatthePCIlogichasahighprobabilityforchange,orwaitinguntilthedesignrequirementsarefirm-potentiallyimpactingtheendproduct'sschedule.WithbothprogrammablelogicandASICworkingtogetheronasingledevice,somesituationlikethesecanbeaccommodated.OthersimilarissueslikedifferinggeographicorI/OstandardscouldalsobeincorporatedwithintheFPGAcores,withoutrequiringmaskandfabricationupdatesforeachchange.

10.2EconomicsPlayaRoleinUsingHybridDevices

Whiletechnicalapplicationsareemergingforthehybridarchitecture,itisunlikelythatdesignteamswouldutilizethisnewcapabilityunlessit

isalsoeconomicallyviable.Wewillnowexploretheeconomicsbehindthisnewarchitecture.

TorealizetheperformanceanddensityadvantagesofanASIC,designteamsmustaccepthigherNREandlongerTATthanaFPGA.Unlikeoff-the-shiftFPGA,eachASICdesignrequiresacustomsetofmasksforsiliconfabrication.Thecustommasksetallowscircuitilityandinterconnectionstobetailoredtotherequirementsofeachuniqueapplication---yieldinghighperformanceanddensity.However,thecostofthemasksetsisrapidlyincreasing（nearlydoublingwitheachsuccessivetechnologynode）.asaresult,maskcostsarebecomingassignificantportionoftheper-diecostinmanycases.

Forexample,considerthecasewhere'remasksetcosts$1,000,000.Forapplicationswhereonly1,000chiparerequired,eachchipwillover$1000,

sincethemaskcost（plusmanyotherexpenses）mustbeamortizedoverthevolumeofchipsold.AsthevolumeforthissameASICrise,effectivecostofeachdiedecrease..

Conversely,FPGAarestandardproducts,wherethemaskchargesforsmallnumberofdesignpassesareamortizedoveralargenumberofcustomersandchips,sothemaskcostperchipsoldisminimal.Asaresult,foreachtechnologynodethereisavolumethreshold,belowwhichit'morecost-effectivetobuyanFPGAchipvs.asmallerASICchip.TATisanotherprimaryeconomicdriver,havingadirectimpactontime-to-marketformanyapplications.ThetimerequiredforASIClayoutandfabricationistypicallyintherange2-5months---muchlongerthanFPGA,whichgenerallyrequire1-4weeksonceacustomer'sRTLisfir