《微型计算机原理及应用技术》程序代码.docx
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《微型计算机原理及应用技术》程序代码
《微型计算机原理及应用技术》编程程序
目录:
2分频电路
N分频电路(8选一为例)
多进制加法计数器
基本D触发器
数据选择器(四选一)
异步复位可逆计数器
优先编码器
2分频电路
libraryieee;
useieee.std_logic_1164.all;
entityfredvider1is
port(
clock:
instd_logic;
clkout:
outstd_logic
);
end;
architecturebehavioroffredvider1is
signalclk:
std_logic;
begin
process(clock)
begin
ifrising_edge(clock)then
clk<=notclk;
endif;
endprocess;
clkout<=clk;
end;
N分频电路(8选一为例)
libraryieee;
useieee.std_logic_1164.all;
entityfredevider8is
port
(clkin:
instd_logic;
clkout:
outstd_logic);
end;
architecturebhvoffredevider8is
constantn:
integer:
=3;
signalcounter:
integerrange0toN;
signalclk:
std_logic;
begin
process(clkin)
begin
ifrising_edge(clkin)then
ifcounter=nthen
counter<=0;
clk<=notclk;
else
counter<=counter+1;
endif;
endif;
endprocess;
clkout<=clk;
end;
多进制加法计数器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycount2is
port
(cp,res:
instd_logic;
ql,qh:
outstd_logic_vector(3downto0));
end;
architecturebhvofcount2is
signalqnl,qnh:
std_logic_vector(3downto0);
begin
process(cp,res)
begin
ifres='1'thenqnl<="0000";qnh<="0000";
elsifrising_edge(cp)then
ifqnl="0011"andqnh="0010"
thenqnl<="0000";
qnh<="0000";
elsifqnl="1001"thenqnl<="0000";qnh<=qnh+1;
elseqnl<=qnl+1;
endif;
endif;
endprocess;
ql<=qnl;
qh<=qnh;
end;
基本D触发器
libraryieee;
useieee.std_logic_1164.all;
entitydff1is
port(d:
instd_logic;
clk:
instd_logic;
q:
outstd_logic);
end;
architecturebhvofdff1is
signalqn:
std_logic;
begin
process(clk)
begin
ifrising_edge(clk)then
qn<=d;
endif;
endprocess;
q<=qn;
end;
异步复位的D触发器
libraryieee;
useieee.std_logic_1164.all;
entitydff2is
port(D,clk,clr:
instd_logic;
Q:
outstd_logic);
――定义输入、输出端口
endentitydff2;
architectureoneofdff2is
begin
process(clk,D,clr)――进程敏感信号
begin
ifclr='1'then
Q<='0';
Elsifclk'eventandclk='1'then
――时钟触发状态
Q<=D;
endif;
endprocess;
endarchitectureone;
同步复位的D触发器
libraryieee;
useieee.std_logic_1164.all;
entitydff1is
port(D,clk,clr:
instd_logic;Q:
outstd_logic);
――定义输入、输出端口
endentitydff1;
architectureoneofdff1is
begin
process(clk,D,clr)――进程敏感信号
Begin
ifclk'eventandclk=‘1'then――时钟控制优先
ifclr=‘1'then
Q<='0';
else
Q<=D;
endif;
endif;
endprocess;
endarchitectureone;
数据选择器(四选一)
libraryieee;
useieee.std_logic_1164.all;
entitymux4is
port(
clock1,clock2,clock3,clock4:
instd_logic;
sel:
instd_logic_vector(1downto0);
clkout:
outstd_logic
);
end;
architecturedataflowofmux4is
begin
process(sel,clock1,clock2,clock3,clock4)
begin
caseselis
when"00"=>clkout<=clock1;
when"01"=>clkout<=clock2;
when"10"=>clkout<=clock3;
when"11"=>clkout<=clock4;
whenothers=>clkout<='0';
endcase;
endprocess;
end;
异步复位可逆计数器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycount1is
port
(cp,res,dir:
instd_logic;
q:
outstd_logic_vector(3downto0));
end;
architecturebhvofcount1is
signalqn:
std_logic_vector(3downto0);
begin
process(cp,res)
begin
ifres='1'thenqn<="0000";
elsifrising_edge(cp)then
ifdir='0'thenqn<=qn+1;
elseqn<=qn-1;
endif;
endif;
q<=qn;
endprocess;
end;
优先编码器
libraryieee;
useieee.std_logic_1164.all;
entityencoderis
port(
en:
instd_logic;
i:
instd_logic_vector(7downto0);
a:
outstd_logic_vector(2downto0);
idle:
outstd_logic
);
end;
architecturebehaciorofencoderis
begin
process(en,i)
begin
ifen='1'then
ifi(7)='1'then
a<="111";
idle<='0';
elsifi(6)='1'then
a<="110";
idle<='0';
elsifi(5)='1'then
a<="101";
idle<='0';
elsifi(4)='1'then
a<="100";
idle<='0';
elsifi(3)='1'then
a<="011";
idle<='0';
elsifi
(2)='1'then
a<="010";
idle<='0';
elsifi
(1)='1'then
a<="001";
idle<='0';
elsifi(0)='1'then
a<="000";
idle<='0';
else
a<="000";
idle<='1';
endif;
else
a<="000";
idle<='1';
endif;
endprocess;
end;