基于FPGA的SDRAM实验Verilog源代码.docx
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基于FPGA的SDRAM实验Verilog源代码
//megafunctionwizard:
%ALTPLL%
//GENERATION:
STANDARD
//VERSION:
WM1.0
//MODULE:
altpll
//============================================================
//FileName:
clk_ctrl.v
//MegafunctionName（s）:
//altpll
//
//SimulationLibraryFiles（s）:
//altera_mf
//============================================================
//************************************************************
//THISISAWIZARD-GENERATEDFILE.DONOTEDITTHISFILE!
//
//11.0Build20807/03/2011SP1SJFullVersion
//************************************************************
//Copyright（C）1991-2011AlteraCorporation
//YouruseofAlteraCorporation'sdesigntools,logicfunctions
//andothersoftwareandtools,anditsAMPPpartnerlogic
//functions,andanyoutputfilesfromanyoftheforegoing
//（includingdeviceprogrammingorsimulationfiles）,andany
//associateddocumentationorinformationareexpresslysubject
//tothetermsandconditionsoftheAlteraProgramLicense
//SubscriptionAgreement,AlteraMegaCoreFunctionLicense
//Agreement,orotherapplicablelicenseagreement,including,
//withoutlimitation,thatyouruseisforthesolepurposeof
//programminglogicdevicesmanufacturedbyAlteraandsoldby
//Alteraoritsauthorizeddistributors.Pleaserefertothe
//applicableagreementforfurtherdetails.
//synopsystranslate_off
`timescale1ps/1ps
//synopsystranslate_on
moduleclk_ctrl（
areset,
inclk0,
c0,
c1,
c2,
locked）;
inputareset;
inputinclk0;
outputc0;
outputc1;
outputc2;
outputlocked;
`ifndefALTERA_RESERVED_QIS
//synopsystranslate_off
`endif
tri0areset;
`ifndefALTERA_RESERVED_QIS
//synopsystranslate_on
`endif
wire[5:
0]sub_wire0;
wiresub_wire2;
wire[0:
0]sub_wire7=1'h0;
wire[2:
2]sub_wire4=sub_wire0[2:
2];
wire[0:
0]sub_wire3=sub_wire0[0:
0];
wire[1:
1]sub_wire1=sub_wire0[1:
1];
wirec1=sub_wire1;
wirelocked=sub_wire2;
wirec0=sub_wire3;
wirec2=sub_wire4;
wiresub_wire5=inclk0;
wire[1:
0]sub_wire6={sub_wire7,sub_wire5};
altpllaltpll_component（
.areset（areset）,
.inclk（sub_wire6）,
.clk（sub_wire0）,
.locked（sub_wire2）,
.activeclock（）,
.clkbad（）,
.clkena（{6{1'b1}}）,
.clkloss（）,
.clkswitch（1'b0）,
.configupdate（1'b0）,
.enable0（）,
.enable1（）,
.extclk（）,
.extclkena（{4{1'b1}}）,
.fbin（1'b1）,
.fbmimicbidir（）,
.fbout（）,
.fref（）,
.icdrclk（）,
.pfdena（1'b1）,
.phasecounterselect（{4{1'b1}}）,
.phasedone（）,
.phasestep（1'b1）,
.phaseupdown（1'b1）,
.pllena（1'b1）,
.scanaclr（1'b0）,
.scanclk（1'b0）,
.scanclkena（1'b1）,
.scandata（1'b0）,
.scandataout（）,
.scandone（）,
.scanread（1'b0）,
.scanwrite（1'b0）,
.sclkout0（）,
.sclkout1（）,
.vcooverrange（）,
.vcounderrange（））;
defparam
altpll_component.clk0_divide_by=1,
altpll_component.clk0_duty_cycle=50,
altpll_component.clk0_multiply_by=5,
altpll_component.clk0_phase_shift="0",
altpll_component.clk1_divide_by=1,
altpll_component.clk1_duty_cycle=50,
altpll_component.clk1_multiply_by=1,
altpll_component.clk1_phase_shift="0",
altpll_component.clk2_divide_by=1,
altpll_component.clk2_duty_cycle=50,
altpll_component.clk2_multiply_by=5,
altpll_component.clk2_phase_shift="5000",
altpll_pensate_clock="CLK0",
altpll_component.gate_lock_signal="NO",
altpll_component.inclk0_input_frequency=50000,
altpll_component.intended_device_family="CycloneII",
altpll_component.invalid_lock_multiplier=5,
altpll_component.lpm_hint="CBX_MODULE_PREFIX=clk_ctrl",
altpll_component.lpm_type="altpll",
altpll_component.operation_mode="NORMAL",
altpll_component.port_activeclock="PORT_UNUSED",
altpll_component.port_areset="PORT_USED",
altpll_component.port_clkbad0="PORT_UNUSED",
altpll_component.port_clkbad1="PORT_UNUSED",
altpll_component.port_clkloss="PORT_UNUSED",
altpll_component.port_clkswitch="PORT_UNUSED",
altpll_component.port_configupdate="PORT_UNUSED",
altpll_component.port_fbin="PORT_UNUSED",
altpll_component.port_inclk0="PORT_USED",
altpll_component.port_inclk1="PORT_UNUSED",
altpll_component.port_locked="PORT_USED",
altpll_component.port_pfdena="PORT_UNUSED",
altpll_component.port_phasecounterselect="PORT_UNUSED",
altpll_component.port_phasedone="PORT_UNUSED",
altpll_component.port_phasestep="PORT_UNUSED",
altpll_component.port_phaseupdown="PORT_UNUSED",
altpll_component.port_pllena="PORT_UNUSED",
altpll_component.port_scanaclr="PORT_UNUSED",
altpll_component.port_scanclk="PORT_UNUSED",
altpll_component.port_scanclkena="PORT_UNUSED",
altpll_component.port_scandata="PORT_UNUSED",
altpll_component.port_scandataout="PORT_UNUSED",
altpll_component.port_scandone="PORT_UNUSED",
altpll_component.port_scanread="PORT_UNUSED",
altpll_component.port_scanwrite="PORT_UNUSED",
altpll_component.port_clk0="PORT_USED",
altpll_component.port_clk1="PORT_USED",
altpll_component.port_clk2="PORT_USED",
altpll_component.port_clk3="PORT_UNUSED",
altpll_component.port_clk4="PORT_UNUSED",
altpll_component.port_clk5="PORT_UNUSED",
altpll_component.port_clkena0="PORT_UNUSED",
altpll_component.port_clkena1="PORT_UNUSED",
altpll_component.port_clkena2="PORT_UNUSED",
altpll_component.port_clkena3="PORT_UNUSED",
altpll_component.port_clkena4="PORT_UNUSED",
altpll_component.port_clkena5="PORT_UNUSED",
altpll_component.port_extclk0="PORT_UNUSED",
altpll_component.port_extclk1="PORT_UNUSED",
altpll_component.port_extclk2="PORT_UNUSED",
altpll_component.port_extclk3="PORT_UNUSED",
altpll_component.valid_lock_multiplier=1;
endmodule
//============================================================
//CNXfileretrievalinfo
//============================================================
//Retrievalinfo:
PRIVATE:
ACTIVECLK_CHECKSTRING"0"
//Retrievalinfo:
PRIVATE:
BANDWIDTHSTRING"1.000"
//Retrievalinfo:
PRIVATE:
BANDWIDTH_FEATURE_ENABLEDSTRING"0"
//Retrievalinfo:
PRIVATE:
BANDWIDTH_FREQ_UNITSTRING"MHz"
//Retrievalinfo:
PRIVATE:
BANDWIDTH_PRESETSTRING"Low"
//Retrievalinfo:
PRIVATE:
BANDWIDTH_USE_AUTOSTRING"1"
//Retrievalinfo:
PRIVATE:
BANDWIDTH_USE_CUSTOMSTRING"0"
//Retrievalinfo:
PRIVATE:
BANDWIDTH_USE_PRESETSTRING"0"
//Retrievalinfo:
PRIVATE:
CLKBAD_SWITCHOVER_CHECKSTRING"0"
//Retrievalinfo:
PRIVATE:
CLKLOSS_CHECKSTRING"0"
//Retrievalinfo:
PRIVATE:
CLKSWITCH_CHECKSTRING"1"
//Retrievalinfo:
PRIVATE:
CNX_NO_COMPENSATE_RADIOSTRING"0"
//Retrievalinfo:
PRIVATE:
CREATE_CLKBAD_CHECKSTRING"0"
//Retrievalinfo:
PRIVATE:
CREATE_INCLK1_CHECKSTRING"0"
//Retrievalinfo:
PRIVATE:
CUR_DEDICATED_CLKSTRING"c0"
//Retrievalinfo:
PRIVATE:
CUR_FBIN_CLKSTRING"c0"
//Retrievalinfo:
PRIVATE:
DEVICE_SPEED_GRADESTRING"8"
//Retrievalinfo:
PRIVATE:
DIV_FACTOR0NUMERIC"1"
//Retrievalinfo:
PRIVATE:
DIV_FACTOR1NUMERIC"1"
//Retrievalinfo:
PRIVATE:
DIV_FACTOR2NUMERIC"1"
//Retrievalinfo:
PRIVATE:
DUTY_CYCLE0STRING"50.00000000"
//Retrievalinfo:
PRIVATE:
DUTY_CYCLE1STRING"50.00000000"
//Retrievalinfo:
PRIVATE:
DUTY_CYCLE2STRING"50.00000000"
//Retrievalinfo:
PRIVATE:
EFF_OUTPUT_FREQ_VALUE0STRING"100.000000"
//Retrievalinfo:
PRIVATE:
EFF_OUTPUT_FREQ_VALUE1STRING"20.000000"
//Retrievalinfo:
PRIVATE:
EFF_OUTPUT_FREQ_VALUE2STRING"100.000000"
//Retrievalinfo:
PRIVATE:
EXPLICIT_SWITCHOVER_COUNTERSTRING"0"
//Retrievalinfo:
PRIVATE:
EXT_FEEDBACK_RADIOSTRING"0"
//Retrievalinfo:
PRIVATE:
GLOCKED_COUNTER_EDIT_CHANGEDSTRING"1"
//Retrievalinfo:
PRIVATE:
GLOCKED_FEATURE_ENABLEDSTRING"1"
//Retrievalinfo:
PRIVATE:
GLOCKED_MODE_CHECKSTRING"0"
//Retrievalinfo:
PRIVATE:
GLOCK_COUNTER_EDITNUMERIC"1048575"
//Retrievalinfo:
PRIVATE:
HAS_MANUAL_SWITCHOVERSTRING"1"
//Retrievalinfo:
PRIVATE:
INCLK0_FREQ_EDITSTRING"20.000"
//Retrievalinfo:
PRIVATE:
INCLK0_FREQ_UNIT_COMBOSTRING"MHz"
//Retrievalinfo:
PRIVATE:
INCLK1_FREQ_EDITSTRING"100.000"
//Retrievalinfo:
PRIVATE:
INCLK1_FREQ_EDIT_CHANGEDSTRING"1"
//Retrievalinfo:
PRIVATE:
INCLK1_FREQ_UNIT_CHANGEDSTRING"1"
//Retrievalinfo:
PRIVATE:
INCLK1_FREQ_UNIT_COMBOSTRING"MHz"
//Retrievalinfo:
PRIVATE:
INTENDED_DEVICE_FAMILYSTRING"CycloneII"
//Retrievalinfo:
PRIVATE:
INT_FEEDBACK__MODE_RADIOSTRING"1"
//Retrievalinfo:
PRIVATE:
LOCKED_OUTPUT_CHECKSTRING"1"
//Retrievalinfo:
PRIVATE:
LONG_SCAN_RADIOSTRING"1"
//Retrievalinfo:
PRIVATE:
LVDS_MODE_DATA_RATESTRING"NotAvailable"
//Retrievalinfo:
PRIVATE:
LVDS_MODE_DATA_RATE_DIRTYNUMERIC"0"
//Retrievalinfo:
PRIVATE:
LVDS_PHASE_SHIFT_UNIT0STRING"deg"
//Retrievalinfo:
PRIVATE:
LVDS_PHASE_SHIFT_UNIT1STRING"deg"
//Retrievalinfo:
PRIVATE:
LVDS_PHASE_SHIFT_UNIT2STRING"deg"
//Retrievalinfo:
PRIVATE:
MIG_DEVICE_SPEED_GRADESTRING"Any"
//Retrievalinfo:
PRIVATE:
MIRROR_CLK0STRING"0"
//Retrievalinfo:
PRIVATE:
MIRROR_CLK1STRING"0"
//Retrievalinfo:
PRIVATE:
MIRROR_CLK2STRING"0"
//Retrievalinfo:
PRIVATE:
MULT_FACTOR0NUMERIC"5"
//Retrievalinfo:
PRIVATE:
MULT_FACTOR1NUMERIC"1"
//Retrievalinfo:
PRIVATE:
MULT_FACTOR2NUMERIC"5"
//Retrievalinfo:
PRIVATE:
NORMAL_MODE_RADIOSTRING"1"
//Retrievalinfo:
PRIVATE:
OUTPUT_FREQ0STRING"100.00000000"
//Retrievalinfo:
PRIVATE:
OUTPUT_FREQ1STRING"100.00000000"
//Retrievalinfo:
PRIVATE:
OUTPUT_FREQ2STRING"100.00000000"
//Retrievalinfo:
PRIVATE:
OUTPUT_FREQ_MODE0STRING"0"
//Retrievalinfo:
PRIVATE:
OUTPUT_FREQ_MODE1STRING"0"
//Retrievalinfo:
PRIVATE:
OUTPUT_FREQ_MODE2STRING"0"
//Retrievali
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