16位模型机的设计Word格式.docx

资源描述

16位模型机的设计Word格式.docx

《16位模型机的设计Word格式.docx》由会员分享，可在线阅读，更多相关《16位模型机的设计Word格式.docx（20页珍藏版）》请在冰点文库上搜索。

16位模型机的设计Word格式.docx

BRANCHI

无条件转移到由立即数指定的地址

00110

BRANCHGTI

如果源寄存器内容大于目的寄存器的内容，则转移到由立即数指定的地址

00111

INC

寄存器内容加1指令

依据以上设计的指令系统，则完成数据块复制的程序如下：

地址

机器码

功能说明

0000H

0001H

2001H

0010H

LOADIR1，0010H

0002H

0003H

2002H

0030H

LOADIR2，0030H

0004H

0005H

2006H

002FH

LOADIR6，002FH

0006H

080BH

LOADR3，[R1]

0007H

101AH

STORE[R2]，R3

0008H

0009H

300EH

BRANCHGTI0000

如果R1大于R6，则转向地址0000

000AH

3801H

INCR1

000BH

3802H

INCR2

000CH

000DH

2800H

BRANCHI0006H

转向00006H，实现循环

3.VHDL设计

一、程序包：

说明运算器的功能、移动寄存器的操作、比较器的比较类型和用于CPU控制的状态类型。

libraryieee;

usecpu_libis

subtypet_shiftisunsigned（3downto0）;

constantshftpass:

unsigned（3downto0）:

0000"

;

constantsftl:

0001"

constantsftr:

0010"

constantrotl:

0011"

constantrotr:

0100"

subtypet_aluisunsigned（3downto0）;

constantalupass:

constantandOp:

constantorOp:

constantnotOp:

constantxorOp:

constantplus:

0101"

constantalusub:

0110"

constantinc:

0111"

constantdec:

1000"

constantzero:

1001"

subtypet_compisunsigned2downto0）;

constanteq:

unsigned（2downto0）:

000"

constantneq:

001"

constantgt:

010"

constantgte:

011"

constantlt:

100"

constantlte:

101"

subtypet_regisstd_logic_vector（2downto0）;

typestateis（reset1,reset2,reset3,reset4,reset5,reset6,execute,nop,load,store,move,

load2,load3,load4,store2,store3,store4,move2,move3,move4,

incPc,incPc2,incPc3,incPc4,incPc5,incPc6,loadPc,loadPc2,loadPc3,loadPc4,

bgtI2,bgtI3,bgtI4,bgtI5,bgtI6,bgtI7,bgtI8,bgtI9,bgtI10,braI2,braI3,braI4,braI5,braI6,

loadI2,loadI3,loadI4,loadI5,loadI6,inc2,inc3,inc4）;

subtypebit16isstd_logic_vector（15downto0）;

endcpu_lib;

二、基本部件的设计

1）运算器的设计

功能

libraryieee;

usealuis

port（a,b:

inbit16;

sel:

int_alu;

outbit16）;

endalu;

architecturert1ofaluis

begin

process（a,b,sel）

caseselis

whenalupass=>

=aafter1ns;

whenandop=>

=aandbafter1ns;

whenorop=>

=aorbafter1ns;

whenxorop=>

=axorbafter1ns;

whennotop=>

=notaafter1ns;

whenplus=>

=a+bafter1ns;

whenalusub=>

=a-bafter1ns;

wheninc=>

=a+"

0000000000000001"

after1ns;

whendec=>

=a-"

whenzero=>

0000000000000000"

whenothers=>

endcase;

endprocess;

endrt1;

2）比较器

usecompis

port（a,b:

int_comp;

compout:

outbit）;

endcomp;

architecturert1ofcompis

process（a,b,sel）

caseselis

wheneq=>

ifa=bthencompout<

elsecompout<

endif;

whenneq=>

ifa/=bthencompout<

whengt=>

ifa>

bthencompout<

whengte=>

=bthencompout<

whenlt=>

ifa<

whenlte=>

whenothers=>

compout<

3）移位寄存器

useshiftis

port（a:

int_shift;

endshift;

architecturert1ofshiftis

process（a,sel）

whenshftpass=>

=aafter1ns;

whensftl=>

=a（14downto0）&

after1ns;

whensftr=>

a（15downto1）after1ns;

whenrotl=>

a（15）after1ns;

whenrotr=>

=a（0）&

whenothers=>

4）寄存器

useregis

clk:

instd_logic;

endreg;

architecturert1ofregis

process

waituntilclk'

eventandclk='

5）寄存器组

useregarrayis

port（data:

int_reg;

en,clk:

endregarray;

architecturert1ofregarrayis

typet_ramisarray（0to7）ofbit16;

signaltemp_data:

bit16;

process（clk,sel）

variableramdata:

t_ram;

ifclk'

thenramdata（conv_integer（sel））:

=data;

endif;

temp_data<

=ramdata（conv_integer（sel））after1ns;

process（en,temp_data）

ifen='

thenq<

=temp_dataafter1ns;

elseq<

ZZZZZZZZZZZZZZZZ"

6）三态寄存器

usetriregis

endtrireg;

architecturert1oftriregis

signalval:

begin

waituntilclk'

val<

=a;

process（en,val）

=valafter1ns;

elsifen='

elseq<

XXXXXXXXXXXXXXXX"

7）控制器

采用状态机实现

libraryIEEE;

usecontrolis

port（clock,reset,compout:

instrReg:

progCntrWr,progCntrRd,addrRegWr,outRegWr,outRegRd:

outstd_logic;

shiftSel:

outt_shift;

aluSel:

outt_alu;

compSel:

outt_comp;

opRegRd,opRegWr,instrWr,regRd,regWr,rw,vma:

regSel:

outt_reg）;

endcontrol;

architecturertlofcontrolis

signalcurrent_state,next_state:

state;

process（current_state,instrReg,compout）

begin

progCntrWr<

progCntrRd<

addrRegWr<

outRegWr<

outRegRd<

shiftSel<

=shftpass;

aluSel<

=alupass;

compSel<

=eq;

opRegRd<

opRegWr<

instrWr<

regSel<

regRd<

regWr<

rw<

vma<

casecurrent_stateis

whenreset1=>

aluSel<

=zeroafter1ns;

shiftSel<

=shftpass;

next_state<

=reset2;

whenreset2=>

=zero;

outRegWr<

=reset3;

whenreset3=>

outRegRd<

=reset4;

whenreset4=>

progCntrWr<

addrRegWr<

=reset5;

whenreset5=>

vma<

next_state<

=reset6;

whenreset6=>

rw<

instrWr<

=execute;

whenexecute=>

caseinstrReg（15downto11）is

when"

00000"

=incPc;

--nop

when"

00001"

regSel<

=instrReg（5downto3）;

regRd<

next_state<

=load2;

00010"

=instrReg（2downto0）;

=store2;

--store

00011"

=alupass;

shiftSel<

=move2;

00100"

progcntrRd<

alusel<

=inc;

shiftsel<

=loadI2;

00101"

=braI2;

00110"

=bgtI2;

--BranchGTImm

when"

00111"

shiftsel<

=inc2;

whenothers=>

next_state<

=incPc;

endcase;

whenload2=>

=instrReg（5downto3）;

regRd<

addrregWr<

=load3;

whenload3=>

=load4;

whenload4=>

=instrReg（2downto0）;

regWr<

whenstore2=>

=store3;

whenstore3=>

=store4;

whenstore4=>

whenmove2=>

aluSel<

shiftsel<

outRegWr<

=move3;

whenmove3=>

outRegRd<

=move4;

whenmove4=>

regSel<

whenloadI2=>

progcntrRd<

alusel<

=inc;

shiftsel<

outregWr<

=loadI3;

whenloadI3=>

outregRd<

=loadI4;

whenloadI4=>

progcntrWr<

addrregWr<

=loadI5;

whenloadI5=>

=loadI6;

whenloadI6=>

whenbraI2=>

=braI3;

whenbraI3=>

=braI4;

whenbraI4=>

outregRd<

=braI5;

whenbraI5=>

=braI6;

whenbraI6=>

progcntrWr<

=loadPc;

whenbgtI2=>

opRegWr<

=bgtI3;

whenbgtI3=>

opRegRd<

compsel<

=gt;

=bgtI4;

whenbgtI4=>

compsel<

ifcompout='

thennext_state<

=bgtI5;

elsenext_state<

endif;

whenbgtI

展开阅读全文