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新型晶体管同或异或门电压控制环振荡器设计外文+文献翻译精品

机械与电气工程学院

毕业设计（论文）外文翻译

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机电学院

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2013年10月31日

VoltageControlledRingOscillatorDesignwithNovel3TransistorsXNOR/XORGates

ManojKumar1,SandeepKumarArya1,SujataPandey2

1DepartmentofElectronics&CommunicationEngineeringGuruJambheshwar,UniversityofScience&Technology,Hisar,India

2DepartmentofElectronics&CommunicationEngineering,AmityUniversity,Noida,India

E-mail:

manojtaleja@gjust.org

ReceivedApril14,2011;revisedMay6,2011;acceptedMay13,2011

Abstract

Inpresentwork,improveddesignsforvoltagecontrolledringoscillators（VCO）usingthreetransistorsXNOR/XORgateshavebeenpresented.Supplyvoltagehasbeenvariedfrom[1.8-1.2]Vinproposedde-signs.Infirstmethod,theVCOdesignusingthreeXNORdelaycellsshowsfrequencyvariationof[1.900-0.964]GHzwith[279.429-16.515]μWpowerconsumptionvariation.VCOdesignedwithfiveXNORde-laycellsshowsfrequencyvariationof[1.152-0.575]GHzwithvaryingpowerconsumptionof[465.715-27.526]μW.InthesecondmethodVCOhavingthreeXORstagesshowsfrequencyvariation[1.9176-1.029]GHzwithpowerconsumptionvariationfrom[296.393-19.051]μW.AfivestageXORbasedVCOdesignshowsfrequencyvariation[1.049-0.565]GHzwithpowerconsumptionvariationfrom[493.989-31.753]μW.SimulationshavebeenperformedbyusingSPICEbasedonTSMC0.18μmCMOStechnology.Powercon-sumptionandoutputfrequencyrangeofproposedVCOshavebeencomparedwithearlierreportedcircuitsandproposedcircuit’sshowsimprovedperformance.

Keywords:

CMOS,DelayCell,LowPower,VCO,XORandXNORGates

1.Introduction

ThePhaselockedloops（PLL）arewidelyusedcircuitcomponentindatatransmissionsystemsandhaveexten-siveapplicationsindatamodulation,demodulationandmobilecommunication.Voltagecontroloscillators（VCO）arethecriticalandnecessarybuildingblocksofthesePLLsystems.TwowidelyusedVCOstypesareLCtankbasedandCMOSringcircuits.CombinationofinductorandcapacitorconsumeslargelayoutareainLCtankbasedoscillators[1-3].CMOSringbasedoscillatorshaveadvantagesduetoeaseofcontrollingtheoutputfrequencyandnorequirementforonchipinductors[4,5].CMOSbasedringoscillatorsareeasiertointegrateandalsogiveswidetuningrange.Duetoflexibilityofonchipintegration,CMOSbasedringoscillatorshavebe-comeessentialbuildingblocksinvariousbatteryoper-atedmobilecommunicationsystems.Risingrequirementofportabledeviceslikecellularphones,notebooks,per-sonalcommunicationdeviceshaveaggressivelyen-hancedattentionforpowersavinginthesedevices.Pow-erconsumptioninverylargescaleintegration（VLSI）systemsincludesdynamic,staticpowerandleakagepowerconsumption.Dynamicpowerconsumptionre-sultsfromswitchingofloadcapacitancebetweentwodifferentvoltagesanddependentonfrequencyofopera-tion.Staticpoweriscontributedbydirectpathshortcir-cuitscurrentsbetweensupply（Vdd）andground（Vss）anditisdependentonleakagecurrentscomponents[6,7].VCOsbeingthemajorcomponentsinPLLsystemandisresponsibleformostofthepowerconsumption.Somedrawbackofringbasedoscillatorsincludeslargepowerconsumption,phasenoiseandthelimitofhighestachievablefrequency.InmodernVCOsdesignpowerconsumptionandoutputfrequencyrangearesignificantperformancemetrics[8-13].Aringoscillatorconsistofdelaystages,withoutputoflaststagefedbacktoinputoffirststage.AVCOblockdiagramwithsingleendedN-delaystagesisshowninFigure1.

Theringmustprovideaphaseshiftof2πandunityvoltagegainforoscillationoccurrence.Eachdelaycellalsogivesaphaseshiftofπ/N,whereNisnumberofdelaystages.Theremainingπphaseshiftisprovidedbydcinversionusingtheinverterdelaycells.Forsingleendedoscillatordesigntheoddnumbersofdelaystagearerequiredfordcinversion.FrequencyofoscillationwithN-singleendeddelaystagesisgivenbyoffo=1/（2Ntd）,whereNisthenumberofdelaystagesandtdisdelayofeachstage[9,14].DelaystagesarethebasicbuildingblocksinanyVCOdesignandimproveddesignofthesedelaycellswillimprovetheoverallperform-ancesofVCO.VarioustypesofdelaycellshavebeenreportedforVCOdesignincludingmultiple-feed-backloops,dual-delaypathsandsingleendeddelays.Thesedelaycellshavebeenimplementedbyvariousap-proacheslikesimpleinverterstage,latches,crosscou-pledcellsetc.[15-18].

InpresentworkmodifiedVCOscircuitswiththreetransistorXNOR/XORdelaycellshavebeenpresentedwithreducedthepowerconsumptionandwideoutputfrequencyrange.Thepaperisorganizedasfollows:

InSection2three&fivestagesXNOR/XORbasedringVCOshavebeenpresented.InSection3resultsforthethreeproposedVCOshavebeenobtainedandcompari-sonswithearlierreportedstructureshavebeenmade.Finally,inSection4conclusionshavebeendrawn.

2.SystemDescription

ThefrequencyofsingleendedringVCOisdependentonthedelayprovidedbytheeachdelaycell.Inthepro-poseddesignsnewdelaycellsbasedonthreetransistorXNOR/XORgateshavebeenused.InverteroperationhasbeenimplementedbyXNOR/XORgates.DirectpathbetweenVddandgroundhasbeeneliminatedinproposeddelaycells,duetowhichleakagepowerisreducedandthedesignsarepowerefficient.Thecircuitshavebeendesignedin0.18μmCMOStechnologywithsupplyvol-tageof1.8V.Supplyvoltage/controlvoltagehasbeenvariedfrom1.8to1.2Vforobtainingtheoutputfre-quencyatdifferentsupplyvoltages.

FirstproposeddelaycellisshowninFigure2.XNORdelaystageismadeupoftwoNMOStransistorsandonePMOStransistor.OutoftwoinputterminalofXNORgate,oneisconnectedtogroundandsignalisappliedtootherterminal.ThiscircuitsworksasinverterwithouthavingdirectpathbetweenVddandgroundwithsavinginpowerconsumption.Asmallcapacitanceof0.01pfatoutputofeachdelaycellhasbeenincluded.Thegatelengthsofallthreetransistorshavebeentakenas0.18μm.Widths（Wn）ofNMOStransistors（N1&N2）havebeentaken2.5μmand0.5μmrespectively.Width（Wp）fortransistorP1hasbeentakenas1.0μm.OutputfrequencyiscontrolledbyvaryingthesupplyvoltageofXNORdelaystage.ThreeandfivestagesringVCOshavebeendesignedusingproposedXNORdelaycellasshowninFigures3（a）and（b）.

Figure4showsproposedXORdelaycell,whichcon-sistoftwoPMOStransistors（P1&P2）andoneNMOStransistor（N1）.OneinputterminalofXORgateiscon-nectedtocontrolvoltage（Vc）andsignalisappliedtootherterminalsothatcircuitworksasaninverter.Thegatelengthofallthreetransistorshasbeentakenas0.18μminXNORdelaycell.Width（Wn）ofNMOStransistorN1hasbeentaken0.25μm.Width（Wp）forP1&P2transistorshasbeentakenas2.0μm.Outputfrequencyiscontrolledbyvaryingthecontrolvoltage（Vc）ofsecondinputterminalofXORdelaystage.ThreeandfivestagesringVCOshavebeendesignedusingproposedXORdelaycellasshowninFigures5（a）and（b）.

Figure1.BlockdiagramofsingleendedVCO.Figure2.ProposeddelaycellbasedonXNORgate.

（a）（b）

Figure3.（a）3stages,（b）5stagesringVCObasedonXNORgatedelaycell.

Figure4.ProposeddelaycellbasedonXORgate.

Figure5.（a）3stages,（b）5stagesringVCOwithonXORgatedelaycell.

3.ResultsandDiscussions

SimulationshavebeenperformedusingSPICEbasedonTSMC0.18μmtechnologywithsupplyvoltagevaria-tionsfrom[1.8-1.2]V.Table1showstheresultsforthreeandfivestagesVCOsdesignedwithXNORdelaycells.Supply/controlvoltage（Vc）hasbeenvariedfrom[1.8-1.2]V.OutputfrequencyofthreestageVCOshowsvari-ationfrom[1.900-0.964]GHzwithpowerconsumptionvariationof[279.429-16.515]µW.InfivestagesringVCOfrequencyshowsvariationfrom[1.152-0.575]GHzwithvaryingpowerconsumption[465.715-27.526]µW.Figures6（a）and（b）showsfrequencyandpowercon-sumptionvariationforthreeandfivestagesXNORbasedringVCOs.

Figure7showsoutputwaveformforthree&fivestagesXNORVCOsatsupplyvoltageof1.8V.

Table2showsresultsforthreeandfivestagesringVCOsdesignedwithXORdelaycells.Controlvoltageatthesecondinputterminalofdelaycellshasbeenvariedfrom[1.8-1.2]V.InthreestageVCO,outputfrequencyshowsvariation[1.917-1.029]GHzwithvaryingpowerconsumptionof[296.393-19.051]µW.ForfivestageXORVCOfrequencyvariesfrom[1.049-0.565]GHzwithvaryingpowerconsumptionof[493.989-31.753]µW.Figures8（a）and（b）showsfrequencyandpowerconsumptionvariationforthreeandfivestagesXORbasedringVCOs.Figure9showsoutputwaveformforthree&fivestagesXORbasedVCOatsupplyvoltageof1.8V.

4.Conclusions

InreportedworkimprovedpowerefficientdesignsforthreeandfivestagesCMOSringVCOshavebeenpre-sented.InfirstmethodologydesignwithXNORdelaystageshavebeenpresented.ThreestagesVCOwithXNORshowsfrequencyvariation[1.900-0.964]GHzwithdevia-tioninpowerconsumptionfrom[279.429-16.515]µW.FivestagesXNORdelaybasedVCOgivesoutputfre-quencyrange[1.152-0.575]GHzwithpowerconsump-tionvariation[465.715-27.526]µW.Inthesecondme-thodologyVCOdesignedwiththreestagesXORbaseddelaycellshowsfrequencyvariation[1.917-1.029]GHzwithpowerconsumptionvariation[296.393-19.051]µW.FinallytheVCOdesignedwithfivestagesXORdelaycellsshowsfrequencyvariation[1.049-0.565]GHzwithpowerconsumptionvariation[493.989-31.753]µW.Proposeddesignshavebeencomparedwithpreviou