CPU designWord下载.docx

CPU designWord下载.docx

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clk

clocksignal

Thesignalfromoneelementtoeachotherisdefinedasfollowed:

MBR

Signals

functions

IN

ACCMBR[15..0]

receivethedatafromACC

PC[7..0]

receivetheinstructionaddressfromPC

BRMBR[15..0]

receivethedatafromBR

RAMin[15..0]

receivethedatafromRAM

OUT

RAMout

sendthedatatoRAM

sendthedatatoBR,PC,MARandIR

WR

asignaltoRAMtodeterminereadingorwriting

MAR

MBR[15..0]

receivetheaddressofdatafromMBR

receivetheaddressofinstructionfromPC

SSMAR[7..0]

receivetheaddressofstack

RAMadd[7..0]

sendtheaddresstoRAM

PC

receivetheaddressofnextinstructionfromMBR

sendtheaddressofinstructiontoMAR

IR

receiveinstructionsfromMBR

IR[7..0]

sendinstructionstoCU

BR

receivedatafromMBR

BR[15..0]

senddatatoACCandALU

senddatatoMBR

ACC

ALUACC[15..0]

receivedatafromALU

receivedatafromBR

ACC[15..0]

senddatatoACC

CU

receiveinstructionsfromBR

flagsCU[7..0]

receiveflagsfromFlags

s

asignalfromALUtoproceedCU

ROM[4..0]

sendtheaddressofM-instructioninROM

ALUctl[3..0]

acontrolsignaltoALUtodeterminetheoperate

Thesimplemicro-instructionsetinROMisdesignedasfollowed:

Micro-I

NUM（HEX）

Meanings

c0

·

0000

nooperation

c1

0001

MBR<

-PC

c2

0002

MAR<

c3

0004

PC<

-MBR

c4

0008

IR<

-MBR;

BR<

c5

0010

-RAM

c6

0020

ALU<

-BR

c7

0040

-ACC

c8

0080

c9

0100

ACC<

-ALU

c10

0200

c11

0400

c12

0800

RAM<

c13

1000

-PC+1

c14

2000

c15

4000

-SS

c16

8000

SS<

-SS+1

Flags

ALUflags[7..0]

receiveflagsfromALU

flagsALU[7..0]

sendflagstoALU

sendflagstoCU

Theeachbitofflagsisdesignedasfollowed:

CF

whenneedcarry->

1

BF

whenneedborrow->

2

PF

whenshiftACC->

0/1

3

ZF

whenanswer=0->

1

4

OF

whenoverflow->

5

SF*

whenanswerisnegative->

6

IF*

whendisableinterupt->

7

/

Notes:

‘*’meansdoesn’tuseinthisdesign.‘/’meanshasnodefinition.Thesameasfollowed.

SS

sendtheaddressofstacktoMAR

ALU

receivedatafromACC

acontrolsignalformCUtodeterminetheoperate

receiveflagsfromflags

sendtheanswertoACC

sendflagstoflags

asignaltoproceedCU

ThecontrolsignalfromCUtoALUisdesignedasfollowed:

NUM（binary）

　Functions

ADD

plus

ADC

0101

pluswithflags

SUB

0110

subtract

SBB

0111

subtractwithflags

AND

and

OR

1001

or

NOT

1010

not

XOR

1011

xor

SHL

1100

shiftACCtoleft1bit

SHR

1101

shiftACCtoright1bit

SRL

1110

shiftACCtoleft1bit,logic

SRR

1111

shiftACCtoright1bit,logic

MPY

DIV

0011

Asimpleinstructionsetisdesignedasfollowed:

Instruction

Control

（765432）

MicroOpcode（c）

FetchIandD（10）

直接

间接

无

01

10

00

LOADX

000010

410

STOREX

000011

1112

ADDX

001000

467N9

SUBX

001010

ANDX

001100

ORX

001101

NOTX

001110

XORX

001111

011000

7N9

011010

ADCX

001001

SBBX

001011

011001

011011

MPYX

010100

DIVX

010101

JMPGEZX

010001

32

JMPX

010000

HALT

000000

CALLX

100000

11512143

RET

100001

161553

PUSH

100010

151112

POP

100011

16155410

Simulationresults

TheprogramintheRAMiswrittenbeforehandonthebaseofinstructionset.

Program

CALLCAL

LOADA4

MPYA4

DIVA8

CAL:

LOAD10

STOREA4

LOADA2

STOREA3

LOOP:

ADDA3

LOADA3

SUBA1

JMPGEZLOOP

Thesimulationresultisdisplayasthenextfigure.

Figure1:

TheanswerofplusfromonetoahundrediswrittentoRAM

Figure2:

Thefirststepoftheprogram“CALL50”

Figure3:

Begintocalculateplusfromonetoahundred

Figure4:

Calculating13BAmultiply13BA

Figure5:

Calculating13BAdivide0008

Figure6:

HALTandwaitforaresetsignal

ConclusionsandDiscussions:

1.IsthePOCyoudesigninaccordwiththetheory?

Yes,mydesignofCPUcanshowthebasicfunctionofarealCPUandsimulateawholeprogram.

2.Arethereanyplacesyoucanrevisetoimproveyourdesign?

Toimprovemydesign,IcanoptimizethedesignofALU.Intheresentdesign,therearesometemporaryregistersintheALU.However,itshouldbeasimplelogicelectriccircuit.Therefore,IcanrevisetoimprovemydesignbydesigningtheALUagain.

3.Whatarethecharacterizationsofyourdesign?

ThecharacterizationofmydesigncanbeconcludedasdesigningaoverallconnectionfirstanduseVHDLtofillineachelement.TheelementofCUisthemostimportantpartofthewholeprojectanddeterminingthemicrocontrolinstructionisthefirstworktofinishbyme.

4.Whatdoyoulearnfromthisdesign?

IlearnedhowtodesignaprojectandthegrammarofVHDL.Ofcourse,IamfamiliarwithasimpleprocessofaCPU,understandinghowaCPUfetchinstructionsandexecutethemconcludingADD,SUB,JMPandsoon.

Appendix

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_unsigned.all;

entityMBRis

port（

ACC_in:

instd_logic_vector（15downto0）;

PC_in:

instd_logic_vector（7downto0）;

BR_in:

RAM_out:

outstd_logic_vector（15downto0）;

RAM_in:

MBR_out:

ctl:

WR:

outstd_logic;

reset:

instd_logic;

clk:

instd_logic

）;

endMBR;

architecturefunction_MBRofMBRis

begin

process（clk）

variableMBR_t:

std_logic_vector（15downto0）;

variableRAM_t:

variablex:

integerrange0to1;

if（clk='

1'

andclk'

event）then