第二部分程序包.docx

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第二部分程序包.docx

第二部分程序包

第二部分程序包

一STANDARD程序包

二std_logic_1164程序包

三std_logic_arith程序包

四std_logic_unsigned程序包

五std_logic_signed程序包

六numeric_std程序包

七numeric_bit程序包

 

一STANDARD程序包

--ThesvenSTANDARDpackage.

--Thisdesignunitcontainssomespecialtokens,whichareonly

--recognizedbytheanalyzerwhenitisinspecial"bootstrap"mode.

packageSTANDARDis

--predefinedenumerationtypes:

typeBOOLEANis(FALSE,TRUE);

typeBITis('0','1');

typeCHARACTERis(

NUL,SOH,STX,ETX,EOT,ENQ,ACK,BEL,

BS,HT,LF,VT,FF,CR,SO,SI,

DLE,DC1,DC2,DC3,DC4,NAK,SYN,ETB,

CAN,EM,SUB,ESC,FSP,GSP,RSP,USP,

'','!

','"','#','$','%','&',''',

'(',')','*','+',',','-','.','/',

'0','1','2','3','4','5','6','7',

'8','9',':

',';','<','=','>','?

',

'@','A','B','C','D','E','F','G',

'H','I','J','K','L','M','N','O',

'P','Q','R','S','T','U','V','W',

'X','Y','Z','[','\',']','^','_',

'`','a','b','c','d','e','f','g',

'h','i','j','k','l','m','n','o',

'p','q','r','s','t','u','v','w',

'x','y','z','{','|','}','~',DEL,

C128,C129,C130,C131,C132,C133,C134,C135,

C136,C137,C138,C139,C140,C141,C142,C143,

C144,C145,C146,C147,C148,C149,C150,C151,

C152,C153,C154,C155,C156,C157,C158,C159,

'?

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'');

typeSEVERITY_LEVELis(NOTE,WARNING,ERROR,FAILURE);

--predefinednumerictypes:

--DoINTEGERfirsttoaidimplicitdeclarationsof"**".

typeINTEGERisrange-2147483647to2147483647;

type$UNIVERSAL_INTEGERisrange$-to$+;

type$UNIVERSAL_REALisrange$-.to$+.;

function"*"($LEFT:

$UNIVERSAL_REAL;$RIGHT:

$UNIVERSAL_INTEGER)

return$UNIVERSAL_REAL;

function"*"($LEFT:

$UNIVERSAL_INTEGER;$RIGHT:

$UNIVERSAL_REAL)

return$UNIVERSAL_REAL;

function"/"($LEFT:

$UNIVERSAL_REAL;$RIGHT:

$UNIVERSAL_INTEGER)

return$UNIVERSAL_REAL;

typeREALisrange$-.to$+.;

--predefinedtypeTIME:

typeTIMEisrange$-to$+

units

fs;--femtosecond

ps=1000fs;--picosecond

ns=1000ps;--nanosecond

us=1000ns;--microsecond

ms=1000us;--millisecond

sec=1000ms;--second

min=60sec;--minute

hr=60min;--hour;

endunits;

--subtypeusedinternallyforcheckingtimeexpressionsfornon-negativness:

subtype$NATURAL_TIMEisTIMErange0sectoTIME'HIGH;

subtypeDELAY_LENGTHisTIMErange0fstoTIME'HIGH;

--functionthatreturnsthecurrentsimulationtime:

impurefunctionNOWreturnTIME;

--predefinednumericsubtypes:

subtypeNATURALisINTEGERrange0toINTEGER'HIGH;

subtypePOSITIVEisINTEGERrange1toINTEGER'HIGH;

--predefinedarraytypes:

typeSTRINGisarray(POSITIVErange<>)ofCHARACTER;

typeBIT_VECTORisarray(NATURALrange<>)ofBIT;

--typeFILE_OPEN_KINDis(READ_OPEN,WRITE_OPEN,APPEND_OPEN);

typeFILE_OPEN_KINDis(READ_MODE,WRITE_MODE,APPEND_MODE);

typeFILE_OPEN_STATUSis(OPEN_OK,STATUS_ERROR,NAME_ERROR,MODE_ERROR);

attributeFOREIGN:

STRING;

--

--TherestofthispackageisSVENspecificstuffrequiredtomake

--thisimplementationgo.

--Notethatallthingsaredeclareduseleading$characters,sowedon't

--trampletheuser'snamespace.

--

attribute$BUILTIN:

BOOLEAN;

procedure$RTINDEX(I:

NATURAL;FIRSTARG:

INTEGER;PASSAP,SAVEFREGS:

BOOLEAN);

procedure$RTSYMBOL(S:

STRING;FIRSTARG:

INTEGER;PASSAP,SAVEFREGS:

BOOLEAN);

attribute$BUILTINofall:

functionisTRUE;

attribute$BUILTINofall:

procedureisTRUE;

endSTANDARD;

二std_logic_1164程序包

----------------------------------------------------------------------

--

--Title:

std_logic_1164multi-valuelogicsystem

--Library:

Thispackageshallbecompiledintoalibrary

--:

symbolicallynamedIEEE.

--:

--Developers:

IEEEmodelstandardsgroup(par1164)

--Purpose:

Thispackagesdefinesastandardfordesigners

--:

touseindescribingtheinterconnectiondatatypes

--:

usedinvhdlmodeling.

--:

--Limitation:

Thelogicsystemdefinedinthispackagemay

--:

beinsufficientformodelingswitchedtransistors,

--:

sincesucharequirementisoutofthescopeofthis

--:

effort.Furthermore,mathematics,primitives,

--:

timingstandards,etc.areconsideredorthogonal

--:

issuesasitrelatestothispackageandaretherefore

--:

beyondthescopeofthiseffort.

--:

--Note:

Nodeclarationsordefinitionsshallbeincludedin,

--:

orexcludedfromthispackage.The"packagedeclaration"

--:

definesthetypes,subtypesanddeclarationsof

--:

std_logic_1164.Thestd_logic_1164packagebodyshallbe

--:

consideredtheformaldefinitionofthesemanticsof

--:

thispackage.Tooldevelopersmaychoosetoimplement

--:

thepackagebodyinthemostefficientmanneravailable

--:

tothem.

--:

----------------------------------------------------------------------

--modificationhistory:

----------------------------------------------------------------------

--version|mod.date:

|

--v4.200|01/02/92|

--v4.200|02/26/92|AddedSynopsysSynthesisComments

--v4.200|06/01/92|Modifiedthe"xnor"stobexnorfunctions.

--||(seeNotebellow)

----------------------------------------------------------------------

--

--Note:

BeforetheVHDL'92languagebeingofficiallyadoptedas

--containingthe"xnor"functions,Synopsyswillsupport

--thexnorfunctions(non-overloaded).

--

--GongWenHuangSynopsys,Inc.

--

--

--librarySYNOPSYS;

--useSYNOPSYS.ATTRIBUTES.ALL;

 

PACKAGEstd_logic_1164IS

-------------------------------------------------------------------

--logicstatesystem(unresolved)

-------------------------------------------------------------------

TYPEstd_ulogicIS('U',--Uninitialized

'X',--ForcingUnknown

'0',--Forcing0

'1',--Forcing1

'Z',--HighImpedance

'W',--WeakUnknown

'L',--Weak0

'H',--Weak1

'-'--Don'tcare

);

--attributeENUM_ENCODINGofstd_ulogic:

typeis"UD01ZD01D";

-------------------------------------------------------------------

--unconstrainedarrayofstd_ulogicforusewiththeresolutionfunction

-------------------------------------------------------------------

TYPEstd_ulogic_vectorISARRAY(NATURALRANGE<>)OFstd_ulogic;

-------------------------------------------------------------------

--resolutionfunction

-------------------------------------------------------------------

FUNCTIONresolved(s:

std_ulogic_vector)RETURNstd_ulogic;

--synopsystranslate_off

--attributeREFLEXIVEofresolved:

functionisTRUE;

--attributeRESULT_INITIAL_VALUEofresolved:

functionisstd_ulogic'POS('Z');

--synopsystranslate_on

 

-------------------------------------------------------------------

--***industrystandardlogictype***

-------------------------------------------------------------------

SUBTYPEstd_logicISresolvedstd_ulogic;

-------------------------------------------------------------------

--unconstrainedarrayofstd_logicforuseindeclaringsignalarrays

-------------------------------------------------------------------

TYPEstd_logic_vectorISARRAY(NATURALRANGE<>)OFstd_logic;

-------------------------------------------------------------------

--commonsubtypes

-------------------------------------------------------------------

SUBTYPEX01ISresolvedstd_ulogicRANGE'X'TO'1';--('X','0','1')

SUBTYPEX01ZISresolvedstd_ulogicRANGE'X'TO'Z';--('X','0','1','Z')

SUBTYPEUX01ISresolvedstd_ulogicRANGE'U'TO'1';--('U','X','0','1')

SUBTYPEUX01ZISresolvedstd_ulogicRANGE'U'TO'Z';--('U','X','0','1','Z')

-------------------------------------------------------------------

--overloadedlogicaloperators

-------------------------------------------------------------------

FUNCTION"and"(l:

std_ulogic;r:

std_ulogic)RETURNUX01;

FUNCTION"nand"(l:

std_ulogic;r:

std_ulogic)RETURNUX01;

FUNCTION"or"(l:

std_ulogic;r:

std_ulogic)RETURNUX01;

FUNCTION"nor"(l:

std_ulogic;r:

std_ulogic)RETURNUX01;

FUNCTION"xor"(l:

std_ulogic;r:

std_ulogic)RETURNUX01;

function"xnor"(l:

std_ulogic;r:

std_ulogic)returnux01;

FUNCTION"not"(l:

std_ulogic)RETURNUX01;

-------------------------------------------------------------------

--vectorizedoverloadedlogicaloperators

-------------------------------------------------------------------

FUNCTION"and"(l,r:

std_logic_vector)RETURNstd_logic_vector;

FUNCTION"and"(l,r:

std_ulogic_vector)RETURNstd_ulogic_vector;

FUNCTION"nand"(l,r:

std_logic_vector)RETURNstd_logic_vector;

FUNCTION"nand"(l,r:

std_ulogic_vector)RETURNstd_ulogic_vector;

FUNCTION"or"(l,r:

std_logic_vector)RETURNstd_logic_vector;

FUNCTION"or"(l,r:

std_ulogic_vector)RETURNstd_ulogic_vector;

FUNCTION"nor"(l,r:

std_logic_vector)RETURNstd_logic_vector;

FUNCTION"nor"(l,r:

std_ulogic_vector)RETURNstd_ulogic_vector;

FUNCTION"xor"(l,r:

std_logic_vector)RETURNstd_logic_vector;

FUNCTION"xor"(l,r:

std_ulogic_vector)RETURNstd_ulogic_vector;

-------------------------------------------------------------------------

--Note:

Thedeclarationandimplementationofthe"xnor"functionis

--specificallycommenteduntilatwhichtimetheVHDLlanguagehasbeen

--officiallyadoptedasconta

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